01d1eb4258
Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917 |
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| .. | ||
| adc-target.h | ||
| audiohw-fiiom3k.c | ||
| backlight-fiiom3k.c | ||
| backlight-target.h | ||
| button-fiiom3k.c | ||
| button-target.h | ||
| i2c-target.h | ||
| installer-fiiom3k.c | ||
| lcd-fiiom3k.c | ||
| nand-fiiom3k.c | ||
| nand-target.h | ||
| power-fiiom3k.c | ||
| powermgmt-target.h | ||
| spl-fiiom3k.c | ||
| spl-target.h | ||