42 lines
1.7 KiB
C
42 lines
1.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __NAND_TARGET_H__
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#define __NAND_TARGET_H__
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/* The max page size (main + spare) of all NAND chips used by this target */
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#define NAND_MAX_PAGE_SIZE (2048 + 64)
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/* The clock source to use for the SFC controller. Note the SPL has special
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* handling which ignores this choice, so it only applies to bootloader & app.
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*/
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#define NAND_CLOCK_SOURCE X1000_CLK_SCLK_A
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/* The clock speed to use for the SFC controller during chip identification */
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#define NAND_INIT_CLOCK_SPEED 150000000
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/* Initial value to program SFC_DEV_CONF register with */
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#define NAND_INIT_SFC_DEV_CONF \
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jz_orf(SFC_DEV_CONF, CE_DL(1), HOLD_DL(1), WP_DL(1), \
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CPHA(0), CPOL(0), TSH(7), TSETUP(0), THOLD(0), \
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STA_TYPE_V(1BYTE), CMD_TYPE_V(8BITS), SMP_DELAY(1))
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#endif /* __NAND_TARGET_H__ */
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