01d1eb4258
Initializing the clocks in the SPL brings Rockbox in line with how the FiiO M3K's original SPL works. It's likely other X1000 devices do this too. There was a logic error in the previous setup: the code falsely assumed that DDR memory would always be running from MPLL, but it would be switched to APLL by the bootloader. Rockbox would then try to re-init APLL, albeit with the same parameters. Maybe this was the cause of the boot hang on some units. Change-Id: I64064585e491bbdf1e95fe9428c91a9314f2a917
165 lines
4.7 KiB
C
165 lines
4.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2021 Aidan MacDonald
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "spl-x1000.h"
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#include "gpio-x1000.h"
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#include "clk-x1000.h"
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#include "system.h"
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#include <string.h>
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/* Boot select button state must remain stable for this duration
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* before the choice will be accepted. Currently 100ms.
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*/
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#define BTN_STABLE_TIME (100 * (X1000_EXCLK_FREQ / 4000))
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static const char normal_cmdline[] = "mem=64M@0x0\
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no_console_suspend\
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console=ttyS2,115200n8\
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lpj=5009408\
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ip=off\
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init=/linuxrc\
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ubi.mtd=3\
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root=ubi0:rootfs\
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ubi.mtd=4\
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rootfstype=ubifs\
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rw\
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loglevel=8";
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static const char recovery_cmdline[] = "mem=64M@0x0\
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no_console_suspend\
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console=ttyS2,115200n8\
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lpj=5009408\
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ip=off";
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const struct spl_boot_option spl_boot_options[] = {
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{
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/* Rockbox: the first unused NAND page is 26 KiB in, and the
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* remainder of the block is unused, giving us 102 KiB to use.
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*/
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.nand_addr = 0x6800,
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.nand_size = 0x19800,
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.load_addr = 0x80003ff8, /* first 8 bytes are bootloader ID */
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.exec_addr = 0x80004000,
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.cmdline = NULL,
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},
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{
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/* Original firmware */
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.nand_addr = 0x20000,
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.nand_size = 0x400000,
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.load_addr = 0x80efffc0,
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.exec_addr = 0x80f00000,
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.cmdline = normal_cmdline,
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},
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{
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/* Recovery image */
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.nand_addr = 0x420000,
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.nand_size = 0x500000,
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.load_addr = 0x80efffc0,
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.exec_addr = 0x80f00000,
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.cmdline = recovery_cmdline,
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},
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};
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void spl_error(void)
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{
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const int pin = (1 << 24);
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/* Turn on button light */
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jz_clr(GPIO_INT(GPIO_C), pin);
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jz_set(GPIO_MSK(GPIO_C), pin);
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jz_clr(GPIO_PAT1(GPIO_C), pin);
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jz_set(GPIO_PAT0(GPIO_C), pin);
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while(1) {
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/* Turn it off */
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mdelay(100);
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jz_set(GPIO_PAT0(GPIO_C), pin);
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/* Turn it on */
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mdelay(100);
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jz_clr(GPIO_PAT0(GPIO_C), pin);
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}
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}
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int spl_get_boot_option(void)
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{
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const uint32_t pinmask = (1 << 17) | (1 << 19);
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uint32_t pin = 1, lastpin = 0;
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uint32_t deadline = 0;
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/* Configure the button GPIOs as inputs */
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gpio_config(GPIO_A, pinmask, GPIO_INPUT);
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/* Poll the pins for a short duration to detect a keypress */
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do {
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lastpin = pin;
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pin = ~REG_GPIO_PIN(GPIO_A) & pinmask;
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if(pin != lastpin) {
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/* This will always be set on the first iteration */
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deadline = __ost_read32() + BTN_STABLE_TIME;
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}
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} while(__ost_read32() < deadline);
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/* Play button boots original firmware */
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if(pin == (1 << 17))
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return SPL_BOOTOPT_ORIG_FW;
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/* Volume up boots recovery */
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if(pin == (1 << 19))
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return SPL_BOOTOPT_RECOVERY;
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/* Default is to boot Rockbox */
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return SPL_BOOTOPT_ROCKBOX;
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}
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void spl_handle_pre_boot(int bootopt)
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{
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/* Move system to EXCLK so we can manipulate the PLLs */
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clk_set_ccr_mux(CLKMUX_SCLK_A(EXCLK) | CLKMUX_CPU(SCLK_A) |
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CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A));
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clk_set_ccr_div(1, 1, 1, 1, 1);
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/* Enable APLL @ 1008 MHz (24 MHz EXCLK * 42 = 1008 MHz) */
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jz_writef(CPM_APCR, BS(1), PLLM(41), PLLN(0), PLLOD(0), ENABLE(1));
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while(jz_readf(CPM_APCR, ON) == 0);
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/* System clock setup -- common to Rockbox and FiiO firmware
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* ----
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* CPU at 1 GHz, L2 cache at 500 MHz
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* AHB0 and AHB2 and 200 MHz
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* PCLK at 100 MHz
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* DDR at 200 MHz
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*/
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clk_set_ccr_div(1, 2, 5, 5, 10);
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clk_set_ccr_mux(CLKMUX_SCLK_A(APLL) | CLKMUX_CPU(SCLK_A) |
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CLKMUX_AHB0(SCLK_A) | CLKMUX_AHB2(SCLK_A));
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if(bootopt == SPL_BOOTOPT_ROCKBOX) {
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/* We don't use MPLL in Rockbox, so switch DDR memory to APLL */
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clk_set_ddr(X1000_CLK_SCLK_A, 5);
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/* Turn off MPLL */
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jz_writef(CPM_MPCR, ENABLE(0));
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} else {
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/* TODO: Original firmware needs a lot of other clocks turned on */
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}
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}
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