PCLK doesn't use PLLA as a source but FCLK, so when changing FCLK with
CGU_PROC register, we must change PCLK as well with CGU_PERI register
Operate with 24MHz PCLK (and unboosted FCLK) for Clipv2/Clip+
Use 60MHz on Fuzev2 to keep the display fast enough (still slower than
Fuzev1 though)
µSD seems to function correctly now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25475 a1c6a512-1295-4272-9138-f99709370657
1 more hour of battery life measured on Clip+ : 16h30 with mp3 @192kbps
Fuzev2 frequency isn't changed because the scrollwheel is less
responsive below 60MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25448 a1c6a512-1295-4272-9138-f99709370657
the arm926-ejs doesn't have synchronous/asynchronous/fastbus modes, so
just change CGU_PROC directly
Note: we could use a lower unboosted frequency now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25417 a1c6a512-1295-4272-9138-f99709370657
Instead of modifying CGU_PROC to get 24MHz pclk, just switch to fastbus else Clip+ wouldn't boot
Tested on fuzev1/Clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25413 a1c6a512-1295-4272-9138-f99709370657
Move CLKDIV macros into clock-target.h.
Only enable the necessary interfaces for the 3 clock registers used for SD.
Add MEMSTICK and SDSLOT registers to bottom of register display in View HW info debug page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25309 a1c6a512-1295-4272-9138-f99709370657
Differences remaining:
- list of peripherals reset
- CGU_PROC isn't modified on as3525v2
- CGU_PLLA bits aren't known, but we use a known setting for 240MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24868 a1c6a512-1295-4272-9138-f99709370657
Now making the Fuzev2 bootloader build should be pretty easy
TODO:
- write button driver (FlynDice found all buttons already)
- find button light
- decide if lcd-ssd1303.c must be modified for Clip+ using SSP or forked
- check if backlight code works (I copied Clipv2 code)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24520 a1c6a512-1295-4272-9138-f99709370657
Reuse some code from Clip (LCD) and a lot of code from AS3525
Add a new CPU type : AS3525v2, identical to AS3525 except it's an ARMv5 (arm926-ejs)
SD code still not working
For an unknown reason LCD doesn't work anymore (to be investigated)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24131 a1c6a512-1295-4272-9138-f99709370657
This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz.
Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657
Unaligned memory ops will cause a data abort anyway
Make the check for samplerate at buildtime
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23480 a1c6a512-1295-4272-9138-f99709370657
Adjust SD timeouts accordingly.
Adjust code in debug-as3525.c to display correct frequencies on system/debug/View disk info page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23350 a1c6a512-1295-4272-9138-f99709370657
i2c clock frequency uses pclk as reference, not plla
i2c clock divider is only 10 bits, not 16
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20929 a1c6a512-1295-4272-9138-f99709370657
Inline the 2 uses, and use a preprocessor sanity check for identification frequency
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20924 a1c6a512-1295-4272-9138-f99709370657
Fix CGU_DBOP setting
Set PCLK to the exact frequency (62MHz, not the maximal frequency)
Use a better comment for CLK_DIV macro
Use preprocessor safety checks for clock divider sizes to avoid future mistakes (not for SD_IDENT frequency since that check is handled by mci_set_clock_divider)
Use maximal IDE frequency of 66MHz (like OF), not 90MHz like written in AS3525 datasheet. The IDE chip is somehow linked to internal storage, and a too high frequency could affect the storage driver.
Use the same DBOP frequency of 32MHz for all models (like OF, verified clip, fuze, e200v2 and m200v4), compromise between performance and battery life could be added in the future for each target
Performance increase on Sansa Fuze with DBOP freq. set to 64MHz: +12% fps for lcd_update, +1% fps for yuv
Thanks to daytona955 on the forums for his help
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20923 a1c6a512-1295-4272-9138-f99709370657
Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
