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Sansa AMS: Assume IDE_CLK is used as MCLK for internal SD. We assumed PCLK previously.

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This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz.

Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jack Halpin 2009-12-11 04:53:22 +00:00
parent c0dc3c7a74
commit c03871ab80
3 changed files with 24 additions and 12 deletions
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25
firmware/target/arm/as3525/ata_sd_as3525.c
View file

@ -121,6 +121,10 @@ static struct event_queue sd_queue;
bool sd_enabled = false;
#endif
#if defined(HAVE_MULTIDRIVE)
static bool hs_card = false;
#endif
static struct wakeup transfer_completion_signal;
static volatile unsigned int transfer_error[NUM_VOLUMES];
#define PL180_MAX_TRANSFER_ERRORS 10
@ -347,13 +351,18 @@ static int sd_init_card(const int drive)
sd_parse_csd(&card_info[drive]);
#if defined(HAVE_MULTIDRIVE)
hs_card = (card_info[drive].speed == 50000000) ? true : false;
#endif
/* Boost MCICLK to operating speed */
if(drive == INTERNAL_AS3525)
MCI_CLOCK(drive) = MCI_QUARTERSPEED; /* MCICLK = PCLK/4 = 15.5MHz */
MCI_CLOCK(drive) = MCI_HALFSPEED; /* MCICLK = IDE_CLK/2 = 25 MHz */
#if defined(HAVE_MULTIDRIVE)
else
/* MCICLK = PCLK/2 = 31MHz(HS) or PCLK/4 = 15.5 Mhz (STD)*/
MCI_CLOCK(drive) = ((card_info[drive].speed == 50000000) ?
MCI_HALFSPEED : MCI_QUARTERSPEED);
MCI_CLOCK(drive) = (hs_card ? MCI_HALFSPEED : MCI_QUARTERSPEED);
#endif
/* CMD7 w/rca: Select card to put it in TRAN state */
if(!send_cmd(drive, SD_SELECT_CARD, card_info[drive].rca, MCI_ARG, NULL))
@ -733,10 +742,14 @@ static int sd_transfer_sectors(IF_MD2(int drive,) unsigned long start,
dma_enable_channel(0, dma_buf, MCI_FIFO(drive),
(drive == INTERNAL_AS3525) ? DMA_PERI_SD : DMA_PERI_SD_SLOT,
DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
#if defined(HAVE_MULTIDRIVE)
/*Small delay for writes prevents data crc failures at lower freqs*/
int write_delay = 125;
while(write_delay--);
if((drive == SD_SLOT_AS3525) && !hs_card)
{
int write_delay = 125;
while(write_delay--);
}
#endif
}
else
dma_enable_channel(0, MCI_FIFO(drive), dma_buf,

5
firmware/target/arm/as3525/clock-target.h
View file

@ -118,9 +118,8 @@
#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq
but sd transfers fail on some
players with this limit */
#define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */
//#define AS3525_USB_SEL AS3525_CLK_PLLA /* Input Source */
//#define AS3525_USB_DIV /* div = 1/(n=0?1:2n)*/

6
firmware/target/arm/as3525/debug-as3525.c
View file

@ -185,9 +185,9 @@ int calc_freq(int clk)
if(!(MCI_NAND & (1<<8)))
return 0;
else if(MCI_NAND & (1<<10))
return calc_freq(CLK_PCLK);
return calc_freq(CLK_IDE);
else
return calc_freq(CLK_PCLK)/(((MCI_NAND & 0xff)+1)*2);
return calc_freq(CLK_IDE)/(((MCI_NAND & 0xff)+1)*2);
case CLK_SD_MCLK_MSD:
if(!(MCI_SD & (1<<8)))
return 0;
@ -304,7 +304,7 @@ bool __dbg_hw_info(void)
}
lcd_putsf(0, line++, "SD :%3dMHz %3dMHz",
((AS3525_PCLK_FREQ/ 1000000) /
((AS3525_IDE_FREQ/ 1000000) /
((last_nand & MCI_CLOCK_BYPASS)? 1:(((last_nand & 0xff)+1) * 2))),
calc_freq(CLK_SD_MCLK_NAND)/1000000);
#ifdef HAVE_MULTIDRIVE