I have also made the CMD_CHECK_CRC_BIT unused for now since we do not check any response crc values yet.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25343 a1c6a512-1295-4272-9138-f99709370657
The internal card does not appear to be HS capable, at least not in 2GB clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25316 a1c6a512-1295-4272-9138-f99709370657
The controller only needs to be reset if we had an error to clean up any leftover trash...
Move comment pertaining to retry variable so it's actually nearby.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25315 a1c6a512-1295-4272-9138-f99709370657
Adjust the initial MCI_MASK value to also mask the MCI_INT_RXDR and MCI_INT_TXDR bits as it seems we don't use them for dma transfers.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25314 a1c6a512-1295-4272-9138-f99709370657
Move CLKDIV macros into clock-target.h.
Only enable the necessary interfaces for the 3 clock registers used for SD.
Add MEMSTICK and SDSLOT registers to bottom of register display in View HW info debug page.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25309 a1c6a512-1295-4272-9138-f99709370657
We don't need the post transfer call this way. We check on TRAN state before each partial transfer.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25282 a1c6a512-1295-4272-9138-f99709370657
Especially when using caches we might read the response too fast and get
the response for the previous command instead.
Now Clip+ boots fine with both instruction & data caches enabled, the
delay might need to be lowered though: boot time is a bit longer.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25183 a1c6a512-1295-4272-9138-f99709370657
SD_ALL_SEND_CID was using cardinfo.cid to store the response instead of the temp array used for long responses.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24944 a1c6a512-1295-4272-9138-f99709370657
Remove MCI_HCON read from init_controller() as it now appears unneccesary.
Make sd-init_card() use similar init sequence to the one in sd-as3525.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24903 a1c6a512-1295-4272-9138-f99709370657
I've left in some commented out code for now as this is still a bit experimental.....
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24891 a1c6a512-1295-4272-9138-f99709370657
check all error bits
only signal wakeup on data transfers, not on commands
trim down send_cmd
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24851 a1c6a512-1295-4272-9138-f99709370657
not touching MCI_CTYPE (leaving bus width to 1) gives data transfers
ignore the hardware locked up while error bit for now
remove printf() helper & debug code
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24838 a1c6a512-1295-4272-9138-f99709370657
Disable errors on response timeout since it can happen on SD_SEND_IF_COND
Disable errors on start bit error : it's ignored by the linux driver
No panic on my side with those 2 bits unchecked, but no transfer
completion either.
Note: the Linux driver doesn't implement DMA
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24837 a1c6a512-1295-4272-9138-f99709370657
Reset DMA before transfers and check data transfer over bit in isr
Still no error or data transfer over conditions
Read the correct status register in isr : there is a masked interrupt
status register and a general status register
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24836 a1c6a512-1295-4272-9138-f99709370657
