ade669f0e7
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25189 a1c6a512-1295-4272-9138-f99709370657
791 lines
22 KiB
C
791 lines
22 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2006 Daniel Ankers
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* Copyright © 2008-2009 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h" /* for HAVE_MULTIVOLUME */
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#include "fat.h"
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#include "thread.h"
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#include "hotswap.h"
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#include "system.h"
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#include "kernel.h"
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#include "cpu.h"
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#include <stdio.h>
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#include <stdlib.h>
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#include <string.h>
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#include "as3525v2.h"
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#include "pl081.h" /* DMA controller */
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#include "dma-target.h" /* DMA request lines */
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#include "clock-target.h"
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#include "panic.h"
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#include "stdbool.h"
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#include "ata_idle_notify.h"
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#include "sd.h"
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#include "lcd.h"
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#include <stdarg.h>
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#include "sysfont.h"
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/* command flags */
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#define MCI_NO_RESP (0<<0)
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#define MCI_RESP (1<<0)
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#define MCI_LONG_RESP (1<<1)
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/* controller registers */
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#define SD_BASE 0xC6070000
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#define SD_REG(x) (*(volatile unsigned long *) (SD_BASE+x))
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#define MCI_CTRL SD_REG(0x00)
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/* control bits */
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#define CTRL_RESET (1<<0)
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#define FIFO_RESET (1<<1)
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#define DMA_RESET (1<<2)
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#define INT_ENABLE (1<<4)
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#define DMA_ENABLE (1<<5)
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#define READ_WAIT (1<<6)
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#define SEND_IRQ_RESP (1<<7)
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#define ABRT_READ_DATA (1<<8)
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#define SEND_CCSD (1<<9)
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#define SEND_AS_CCSD (1<<10)
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#define EN_OD_PULLUP (1<<24)
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#define MCI_PWREN SD_REG(0x04) /* power enable */
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#define PWR_CRD_0 (1<<0)
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#define PWR_CRD_1 (1<<1)
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#define PWR_CRD_2 (1<<2)
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#define PWR_CRD_3 (1<<3)
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#define MCI_CLKDIV SD_REG(0x08) /* clock divider */
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/* CLK_DIV_0 : bits 7:0
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* CLK_DIV_1 : bits 15:8
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* CLK_DIV_2 : bits 23:16
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* CLK_DIV_3 : bits 31:24
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*/
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#define MCI_CLKSRC SD_REG(0x0C) /* clock source */
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/* CLK_SRC_CRD0: bits 1:0
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* CLK_SRC_CRD1: bits 3:2
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* CLK_SRC_CRD2: bits 5:4
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* CLK_SRC_CRD3: bits 7:6
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*/
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#define MCI_CLKENA SD_REG(0x10) /* clock enable */
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#define CCLK_ENA_CRD0 (1<<0)
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#define CCLK_ENA_CRD1 (1<<1)
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#define CCLK_ENA_CRD2 (1<<2)
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#define CCLK_ENA_CRD3 (1<<3)
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#define CCLK_LP_CRD0 (1<<16) /* LP --> Low Power Mode? */
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#define CCLK_LP_CRD1 (1<<17)
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#define CCLK_LP_CRD2 (1<<18)
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#define CCLK_LP_CRD3 (1<<19)
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#define MCI_TMOUT SD_REG(0x14) /* timeout */
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/* response timeout bits 0:7
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* data timeout bits 8:31
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*/
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#define MCI_CTYPE SD_REG(0x18) /* card type */
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/* 1 bit per card, set = wide bus */
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#define WIDTH4_CRD0 (1<<0)
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#define WIDTH4_CRD1 (1<<1)
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#define WIDTH4_CRD2 (1<<2)
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#define WIDTH4_CRD3 (1<<3)
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#define MCI_BLKSIZ SD_REG(0x1C) /* block size bits 0:15*/
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#define MCI_BYTCNT SD_REG(0x20) /* byte count bits 0:31*/
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#define MCI_MASK SD_REG(0x24) /* interrupt mask */
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#define MCI_ARGUMENT SD_REG(0x28)
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#define MCI_COMMAND SD_REG(0x2C)
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/* command bits (bits 5:0 are the command index) */
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#define CMD_RESP_EXP_BIT (1<<6)
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#define CMD_RESP_LENGTH_BIT (1<<7)
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#define CMD_CHECK_CRC_BIT (1<<8)
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#define CMD_DATA_EXP_BIT (1<<9)
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#define CMD_RW_BIT (1<<10)
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#define CMD_TRANSMODE_BIT (1<<11)
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#define CMD_SENT_AUTO_STOP_BIT (1<<12)
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#define CMD_WAIT_PRV_DAT_BIT (1<<13)
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#define CMD_ABRT_CMD_BIT (1<<14)
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#define CMD_SEND_INIT_BIT (1<<15)
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#define CMD_SEND_CLK_ONLY (1<<21)
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#define CMD_READ_CEATA (1<<22)
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#define CMD_CCS_EXPECTED (1<<23)
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#define CMD_DONE_BIT (1<<31)
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#define MCI_RESP0 SD_REG(0x30)
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#define MCI_RESP1 SD_REG(0x34)
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#define MCI_RESP2 SD_REG(0x38)
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#define MCI_RESP3 SD_REG(0x3C)
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#define MCI_MASK_STATUS SD_REG(0x40) /* masked interrupt status */
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#define MCI_RAW_STATUS SD_REG(0x44) /* raw interrupt status, also used as
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* status clear */
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/* interrupt bits */
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#define MCI_INT_CRDDET (1<<0) /* card detect */
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#define MCI_INT_RE (1<<1) /* response error */
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#define MCI_INT_CD (1<<2) /* command done */
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#define MCI_INT_DTO (1<<3) /* data transfer over */
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#define MCI_INT_TXDR (1<<4) /* tx fifo data request */
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#define MCI_INT_RXDR (1<<5) /* rx fifo data request */
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#define MCI_INT_RCRC (1<<6) /* response crc error */
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#define MCI_INT_DCRC (1<<7) /* data crc error */
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#define MCI_INT_RTO (1<<8) /* response timeout */
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#define MCI_INT_DRTO (1<<9) /* data read timeout */
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#define MCI_INT_HTO (1<<10) /* data starv timeout */
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#define MCI_INT_FRUN (1<<11) /* fifo over/underrun */
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#define MCI_INT_HLE (1<<12) /* hw locked while error */
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#define MCI_INT_SBE (1<<13) /* start bit error */
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#define MCI_INT_ACD (1<<14) /* auto command done */
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#define MCI_INT_EBE (1<<15) /* end bit error */
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#define MCI_INT_SDIO (0xf<<16)
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/*
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* STATUS register
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* & 0xBA80 = MCI_INT_DCRC | MCI_INT_DRTO | MCI_INT_FRUN | \
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* MCI_INT_HLE | MCI_INT_SBE | MCI_INT_EBE
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* & 8 = MCI_INT_DTO
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* & 0x428 = MCI_INT_DTO | MCI_INT_RXDR | MCI_INT_HTO
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* & 0x418 = MCI_INT_DTO | MCI_INT_TXDR | MCI_INT_HTO
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*/
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#define MCI_ERROR (MCI_INT_RE | MCI_INT_RCRC | MCI_INT_DCRC /*| MCI_INT_RTO*/ \
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| MCI_INT_DRTO | MCI_INT_HTO | MCI_INT_FRUN | MCI_INT_HLE \
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| MCI_INT_SBE | MCI_INT_EBE)
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#define MCI_STATUS SD_REG(0x48)
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#define FIFO_RX_WM (1<<0)
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#define FIFO_TX_WM (1<<1)
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#define FIFO_EMPTY (1<<2)
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#define FIFO_FULL (1<<3)
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#define CMD_FSM_STATE_B0 (1<<4)
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#define CMD_FSM_STATE_B1 (1<<5)
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#define CMD_FSM_STATE_B2 (1<<6)
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#define CMD_FSM_STATE_B3 (1<<7)
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#define DATA_3_STAT (1<<8)
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#define DATA_BUSY (1<<9)
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#define DATA_STAT_MC_BUSY (1<<10)
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#define RESP_IDX_B0 (1<<11)
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#define RESP_IDX_B1 (1<<12)
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#define RESP_IDX_B2 (1<<13)
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#define RESP_IDX_B3 (1<<14)
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#define RESP_IDX_B4 (1<<15)
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#define RESP_IDX_B5 (1<<16)
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#define FIFO_CNT_B00 (1<<17)
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#define FIFO_CNT_B01 (1<<18)
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#define FIFO_CNT_B02 (1<<19)
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#define FIFO_CNT_B03 (1<<20)
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#define FIFO_CNT_B04 (1<<21)
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#define FIFO_CNT_B05 (1<<22)
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#define FIFO_CNT_B06 (1<<23)
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#define FIFO_CNT_B07 (1<<24)
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#define FIFO_CNT_B08 (1<<25)
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#define FIFO_CNT_B09 (1<<26)
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#define FIFO_CNT_B10 (1<<27)
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#define FIFO_CNT_B11 (1<<28)
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#define FIFO_CNT_B12 (1<<29)
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#define DMA_ACK (1<<30)
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#define START_CMD (1<<31)
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#define MCI_FIFOTH SD_REG(0x4C) /* FIFO threshold */
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/* TX watermark : bits 11:0
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* RX watermark : bits 27:16
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* DMA MTRANS SIZE : bits 30:28
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* bits 31, 15:12 : unused
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*/
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#define MCI_FIFOTH_MASK 0x8000f000
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#define MCI_CDETECT SD_REG(0x50) /* card detect */
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#define CDETECT_CRD_0 (1<<0)
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#define CDETECT_CRD_1 (1<<1)
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#define CDETECT_CRD_2 (1<<2)
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#define CDETECT_CRD_3 (1<<3)
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#define MCI_WRTPRT SD_REG(0x54) /* write protect */
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#define MCI_GPIO SD_REG(0x58)
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#define MCI_TCBCNT SD_REG(0x5C) /* transferred CIU byte count (card)*/
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#define MCI_TBBCNT SD_REG(0x60) /* transferred host/DMA to/from bytes (FIFO)*/
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#define MCI_DEBNCE SD_REG(0x64) /* card detect debounce bits 23:0*/
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#define MCI_USRID SD_REG(0x68) /* user id */
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#define MCI_VERID SD_REG(0x6C) /* version id */
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#define MCI_HCON SD_REG(0x70) /* hardware config */
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/* bit 0 : card type
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* bits 5:1 : maximum card index
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* bit 6 : BUS TYPE
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* bits 9:7 : DATA WIDTH
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* bits 15:10 : ADDR WIDTH
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* bits 17:16 : DMA IF
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* bits 20:18 : DMA WIDTH
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* bit 21 : FIFO RAM INSIDE
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* bit 22 : IMPL HOLD REG
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* bit 23 : SET CLK FALSE
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* bits 25:24 : MAX CLK DIV IDX
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* bit 26 : AREA OPTIM
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*/
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#define MCI_BMOD SD_REG(0x80) /* bus mode */
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/* bit 0 : SWR
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* bit 1 : FB
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* bits 6:2 : DSL
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* bit 7 : DE
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* bit 10:8 : PBL
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*/
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#define MCI_PLDMND SD_REG(0x84) /* poll demand */
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#define MCI_DBADDR SD_REG(0x88) /* descriptor base address */
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#define MCI_IDSTS SD_REG(0x8C) /* internal DMAC status */
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/* bit 0 : TI
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* bit 1 : RI
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* bit 2 : FBE
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* bit 3 : unused
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* bit 4 : DU
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* bit 5 : CES
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* bits 7:6 : unused
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* bits 8 : NIS
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* bit 9 : AIS
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* bits 12:10 : EB
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* bits 16:13 : FSM
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*/
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#define MCI_IDINTEN SD_REG(0x90) /* internal DMAC interrupt enable */
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/* bit 0 : TI
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* bit 1 : RI
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* bit 2 : FBE
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* bit 3 : unused
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* bit 4 : DU
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* bit 5 : CES
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* bits 7:6 : unused
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* bits 8 : NI
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* bit 9 : AI
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*/
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#define MCI_DSCADDR SD_REG(0x94) /* current host descriptor address */
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#define MCI_BUFADDR SD_REG(0x98) /* current host buffer address */
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#define MCI_FIFO ((unsigned long *) (SD_BASE+0x100))
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#define UNALIGNED_NUM_SECTORS 10
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static unsigned char aligned_buffer[UNALIGNED_NUM_SECTORS* SD_BLOCK_SIZE] __attribute__((aligned(32))); /* align on cache line size */
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static unsigned char *uncached_buffer = UNCACHED_ADDR(&aligned_buffer[0]);
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static int sd_init_card(void);
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static void init_controller(void);
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static tCardInfo card_info;
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/* for compatibility */
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static long last_disk_activity = -1;
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#define MIN_YIELD_PERIOD 5 /* ticks */
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static long next_yield = 0;
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static long sd_stack [(DEFAULT_STACK_SIZE*2 + 0x200)/sizeof(long)];
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static const char sd_thread_name[] = "ata/sd";
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static struct mutex sd_mtx SHAREDBSS_ATTR;
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static struct event_queue sd_queue;
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#ifndef BOOTLOADER
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bool sd_enabled = false;
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#endif
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static struct wakeup transfer_completion_signal;
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static volatile bool retry;
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static volatile bool data_transfer = false;
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static inline void mci_delay(void) { int i = 0xffff; while(i--) ; }
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void INT_NAND(void)
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{
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MCI_CTRL &= ~INT_ENABLE;
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const int status = MCI_MASK_STATUS;
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MCI_RAW_STATUS = status; /* clear status */
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if(status & MCI_ERROR)
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retry = true;
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if(data_transfer && status & (MCI_INT_DTO|MCI_ERROR))
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wakeup_signal(&transfer_completion_signal);
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MCI_CTRL |= INT_ENABLE;
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}
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static bool send_cmd(const int cmd, const int arg, const int flags,
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unsigned long *response)
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{
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MCI_COMMAND = cmd;
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if(flags & MCI_RESP)
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{
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MCI_COMMAND |= CMD_RESP_EXP_BIT;
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if(flags & MCI_LONG_RESP)
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MCI_COMMAND |= CMD_RESP_LENGTH_BIT;
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}
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if(cmd == SD_READ_MULTIPLE_BLOCK || cmd == SD_WRITE_MULTIPLE_BLOCK)
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{
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MCI_COMMAND |= CMD_WAIT_PRV_DAT_BIT | CMD_DATA_EXP_BIT;
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if(cmd == SD_WRITE_MULTIPLE_BLOCK)
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MCI_COMMAND |= CMD_RW_BIT | CMD_CHECK_CRC_BIT;
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}
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int clkena = MCI_CLKENA;
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MCI_CLKENA = 0;
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MCI_ARGUMENT = arg;
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MCI_COMMAND |= CMD_DONE_BIT;
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int max = 0x40000;
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while(MCI_COMMAND & CMD_DONE_BIT)
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{
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if(--max == 0) /* timeout */
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{
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MCI_CLKENA = clkena;
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return false;
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}
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}
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MCI_CLKENA = clkena;
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if(flags & MCI_RESP)
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{
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int i = 0xff; while(i--) ;
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/* if we read the response too fast we might read the response
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* of the previous command instead */
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if(flags & MCI_LONG_RESP)
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{
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response[3] = MCI_RESP3;
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response[2] = MCI_RESP2;
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response[1] = MCI_RESP1;
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}
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response[0] = MCI_RESP0;
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}
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return true;
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}
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static int sd_init_card(void)
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{
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unsigned long response;
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long init_timeout;
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bool sd_v2 = false;
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/* assume 24 MHz clock / 60 = 400 kHz */
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MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C; /* CLK_DIV_0 : bits 7:0 */
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/* 100 - 400kHz clock required for Identification Mode */
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/* Start of Card Identification Mode ************************************/
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/* CMD0 Go Idle */
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if(!send_cmd(SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
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return -1;
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mci_delay();
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/* CMD8 Check for v2 sd card. Must be sent before using ACMD41
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Non v2 cards will not respond to this command*/
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if(send_cmd(SD_SEND_IF_COND, 0x1AA, MCI_RESP, &response))
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if((response & 0xFFF) == 0x1AA)
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sd_v2 = true;
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/* timeout for initialization is 1sec, from SD Specification 2.00 */
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init_timeout = current_tick + HZ;
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do {
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/* this timeout is the only valid error for this loop*/
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if(TIME_AFTER(current_tick, init_timeout))
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return -2;
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/* app_cmd */
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send_cmd(SD_APP_CMD, 0, MCI_RESP, &response);
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/* ACMD41 For v2 cards set HCS bit[30] & send host voltage range to all */
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if(!send_cmd(SD_APP_OP_COND, (sd_v2 ? 0x40FF8000 : (1<<23)),
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MCI_RESP, &card_info.ocr))
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return -3;
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} while(!(card_info.ocr & (1<<31)) );
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/* CMD2 send CID */
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if(!send_cmd(SD_ALL_SEND_CID, 0, MCI_RESP|MCI_LONG_RESP, card_info.cid))
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return -5;
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/* CMD3 send RCA */
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if(!send_cmd(SD_SEND_RELATIVE_ADDR, 0, MCI_RESP, &card_info.rca))
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return -4;
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/* End of Card Identification Mode ************************************/
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/* CMD9 send CSD */
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if(!send_cmd(SD_SEND_CSD, card_info.rca,
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MCI_RESP|MCI_LONG_RESP, card_info.csd))
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return -5;
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sd_parse_csd(&card_info);
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/* Card back to full speed */
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MCI_CLKDIV &= ~(0xFF); /* CLK_DIV_0 : bits 7:0 = 0x00 */
|
|
|
|
/* CMD7 w/rca: Select card to put it in TRAN state */
|
|
if(!send_cmd(SD_SELECT_CARD, card_info.rca, MCI_NO_RESP, NULL))
|
|
return -6;
|
|
|
|
card_info.initialized = 1;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void sd_thread(void) __attribute__((noreturn));
|
|
static void sd_thread(void)
|
|
{
|
|
struct queue_event ev;
|
|
bool idle_notified = false;
|
|
|
|
while (1)
|
|
{
|
|
queue_wait_w_tmo(&sd_queue, &ev, HZ);
|
|
|
|
switch ( ev.id )
|
|
{
|
|
case SYS_TIMEOUT:
|
|
if (TIME_BEFORE(current_tick, last_disk_activity+(3*HZ)))
|
|
{
|
|
idle_notified = false;
|
|
}
|
|
else
|
|
{
|
|
/* never let a timer wrap confuse us */
|
|
next_yield = current_tick;
|
|
|
|
if (!idle_notified)
|
|
{
|
|
call_storage_idle_notifys(false);
|
|
idle_notified = true;
|
|
}
|
|
}
|
|
break;
|
|
#if 0
|
|
case SYS_USB_CONNECTED:
|
|
usb_acknowledge(SYS_USB_CONNECTED_ACK);
|
|
/* Wait until the USB cable is extracted again */
|
|
usb_wait_for_disconnect(&sd_queue);
|
|
|
|
break;
|
|
case SYS_USB_DISCONNECTED:
|
|
usb_acknowledge(SYS_USB_DISCONNECTED_ACK);
|
|
break;
|
|
#endif
|
|
}
|
|
}
|
|
}
|
|
|
|
static void init_controller(void)
|
|
{
|
|
MCI_PWREN = 0x0; /* power off all cards */
|
|
|
|
MCI_CLKSRC = 0x00; /* All CLK_SRC_CRD set to 0*/
|
|
MCI_CLKDIV = 0x00; /* CLK_DIV_0 : bits 7:0 */
|
|
|
|
MCI_PWREN = PWR_CRD_0; /* power up card 0 (internal) */
|
|
mci_delay();
|
|
|
|
MCI_CTRL |= CTRL_RESET;
|
|
while(MCI_CTRL & CTRL_RESET)
|
|
;
|
|
|
|
MCI_RAW_STATUS = 0xffffffff;
|
|
|
|
MCI_TMOUT = 0xffffffff; /* data b31:8, response b7:0 */
|
|
|
|
MCI_CTYPE = 0x0; /* all cards 1 bit bus for now */
|
|
|
|
MCI_CLKENA = CCLK_ENA_CRD0;
|
|
|
|
MCI_ARGUMENT = 0;
|
|
MCI_COMMAND = CMD_DONE_BIT|CMD_SEND_CLK_ONLY|CMD_WAIT_PRV_DAT_BIT;
|
|
while(MCI_COMMAND & CMD_DONE_BIT)
|
|
;
|
|
|
|
MCI_DEBNCE = 0xfffff; /* default value */
|
|
|
|
MCI_FIFOTH &= MCI_FIFOTH_MASK;
|
|
MCI_FIFOTH |= 0x503f0080;
|
|
|
|
MCI_MASK = 0xffffffff & ~(MCI_INT_ACD|MCI_INT_CRDDET);
|
|
|
|
MCI_CTRL |= INT_ENABLE;
|
|
}
|
|
|
|
int sd_init(void)
|
|
{
|
|
int ret;
|
|
CGU_PERI |= CGU_MCI_CLOCK_ENABLE;
|
|
|
|
CGU_IDE = (1<<7) /* AHB interface enable */ |
|
|
(1<<6) /* interface enable */ |
|
|
((CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) << 2) |
|
|
1; /* clock source = PLLA */
|
|
|
|
CGU_MEMSTICK = (1<<8) | (1<<7) |
|
|
((CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1) << 2) | 1;
|
|
|
|
/* FIXME: divider should be shifted by 2, but doing prevents card
|
|
* initialisation */
|
|
*(volatile int*)(CGU_BASE+0x3C) = (1<<7) |
|
|
(CLK_DIV(AS3525_PLLA_FREQ, 24000000) -1) | 1;
|
|
|
|
wakeup_init(&transfer_completion_signal);
|
|
|
|
VIC_INT_ENABLE |= INTERRUPT_NAND;
|
|
|
|
init_controller();
|
|
ret = sd_init_card();
|
|
if(ret < 0)
|
|
return ret;
|
|
|
|
/* init mutex */
|
|
mutex_init(&sd_mtx);
|
|
|
|
queue_init(&sd_queue, true);
|
|
create_thread(sd_thread, sd_stack, sizeof(sd_stack), 0,
|
|
sd_thread_name IF_PRIO(, PRIORITY_USER_INTERFACE) IF_COP(, CPU));
|
|
|
|
#ifndef BOOTLOADER
|
|
sd_enabled = true;
|
|
sd_enable(false);
|
|
#endif
|
|
return 0;
|
|
}
|
|
|
|
#ifdef STORAGE_GET_INFO
|
|
void sd_get_info(struct storage_info *info)
|
|
{
|
|
info->sector_size=card_info.blocksize;
|
|
info->num_sectors=card_info.numblocks;
|
|
info->vendor="Rockbox";
|
|
info->product = "Internal Storage";
|
|
info->revision="0.00";
|
|
}
|
|
#endif
|
|
|
|
static int sd_wait_for_state(unsigned int state)
|
|
{
|
|
unsigned long response;
|
|
unsigned int timeout = 100; /* ticks */
|
|
long t = current_tick;
|
|
|
|
while (1)
|
|
{
|
|
long tick;
|
|
|
|
if(!send_cmd(SD_SEND_STATUS, card_info.rca,
|
|
MCI_RESP, &response))
|
|
return -1;
|
|
|
|
if (((response >> 9) & 0xf) == state)
|
|
return 0;
|
|
|
|
if(TIME_AFTER(current_tick, t + timeout))
|
|
return -10 * ((response >> 9) & 0xf);
|
|
|
|
if (TIME_AFTER((tick = current_tick), next_yield))
|
|
{
|
|
yield();
|
|
timeout += current_tick - tick;
|
|
next_yield = tick + MIN_YIELD_PERIOD;
|
|
}
|
|
}
|
|
}
|
|
|
|
static int sd_transfer_sectors(unsigned long start, int count, void* buf, bool write)
|
|
{
|
|
int ret = 0;
|
|
|
|
/* skip SanDisk OF */
|
|
start += 0xf000;
|
|
|
|
mutex_lock(&sd_mtx);
|
|
#ifndef BOOTLOADER
|
|
sd_enable(true);
|
|
#endif
|
|
|
|
if (card_info.initialized <= 0)
|
|
{
|
|
ret = sd_init_card();
|
|
if (!(card_info.initialized))
|
|
{
|
|
panicf("card not initialised (%d)", ret);
|
|
goto sd_transfer_error;
|
|
}
|
|
}
|
|
|
|
last_disk_activity = current_tick;
|
|
ret = sd_wait_for_state(SD_TRAN);
|
|
if (ret < 0)
|
|
{
|
|
static const char *st[9] = {
|
|
"IDLE", "RDY", "IDENT", "STBY", "TRAN", "DATA", "RCV", "PRG", "DIS"
|
|
};
|
|
if(ret <= -10)
|
|
panicf("wait for state failed (%s)", st[(-ret / 10) % 9]);
|
|
else
|
|
panicf("wait for state failed");
|
|
goto sd_transfer_error;
|
|
}
|
|
|
|
dma_retain();
|
|
|
|
const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
|
|
|
|
/* Interrupt handler might set this to true during transfer */
|
|
do
|
|
{
|
|
void *dma_buf = aligned_buffer;
|
|
unsigned int transfer = count;
|
|
if(transfer > UNALIGNED_NUM_SECTORS)
|
|
transfer = UNALIGNED_NUM_SECTORS;
|
|
|
|
if(write)
|
|
memcpy(uncached_buffer, buf, transfer * SD_BLOCK_SIZE);
|
|
|
|
retry = false;
|
|
|
|
MCI_BLKSIZ = SD_BLOCK_SIZE;
|
|
MCI_BYTCNT = transfer * SD_BLOCK_SIZE;
|
|
|
|
MCI_CTRL |= (FIFO_RESET|DMA_RESET);
|
|
while(MCI_CTRL & (FIFO_RESET|DMA_RESET))
|
|
;
|
|
|
|
MCI_CTRL |= DMA_ENABLE;
|
|
MCI_MASK = MCI_INT_CD|MCI_INT_DTO|MCI_INT_DCRC|MCI_INT_DRTO| \
|
|
MCI_INT_HTO|MCI_INT_FRUN|MCI_INT_HLE|MCI_INT_SBE|MCI_INT_EBE;
|
|
|
|
MCI_FIFOTH &= MCI_FIFOTH_MASK;
|
|
MCI_FIFOTH |= 0x503f0080;
|
|
|
|
|
|
if(card_info.ocr & (1<<30) ) /* SDHC */
|
|
ret = send_cmd(cmd, start, MCI_NO_RESP, NULL);
|
|
else
|
|
ret = send_cmd(cmd, start * SD_BLOCK_SIZE,
|
|
MCI_NO_RESP, NULL);
|
|
|
|
if (ret < 0)
|
|
panicf("transfer multiple blocks failed (%d)", ret);
|
|
|
|
if(write)
|
|
dma_enable_channel(0, dma_buf, MCI_FIFO, DMA_PERI_SD,
|
|
DMAC_FLOWCTRL_PERI_MEM_TO_PERI, true, false, 0, DMA_S8, NULL);
|
|
else
|
|
dma_enable_channel(0, MCI_FIFO, dma_buf, DMA_PERI_SD,
|
|
DMAC_FLOWCTRL_PERI_PERI_TO_MEM, false, true, 0, DMA_S8, NULL);
|
|
|
|
data_transfer = true;
|
|
wakeup_wait(&transfer_completion_signal, TIMEOUT_BLOCK);
|
|
data_transfer = false;
|
|
|
|
last_disk_activity = current_tick;
|
|
|
|
if(!send_cmd(SD_STOP_TRANSMISSION, 0, MCI_NO_RESP, NULL))
|
|
{
|
|
ret = -666;
|
|
panicf("STOP TRANSMISSION failed");
|
|
goto sd_transfer_error;
|
|
}
|
|
|
|
ret = sd_wait_for_state(SD_TRAN);
|
|
if (ret < 0)
|
|
{
|
|
panicf(" wait for state TRAN failed (%d)", ret);
|
|
goto sd_transfer_error;
|
|
}
|
|
|
|
if(!retry)
|
|
{
|
|
if(!write)
|
|
memcpy(buf, uncached_buffer, transfer * SD_BLOCK_SIZE);
|
|
buf += transfer * SD_BLOCK_SIZE;
|
|
start += transfer;
|
|
count -= transfer;
|
|
}
|
|
} while(retry || count);
|
|
|
|
dma_release();
|
|
|
|
#ifndef BOOTLOADER
|
|
sd_enable(false);
|
|
#endif
|
|
mutex_unlock(&sd_mtx);
|
|
return 0;
|
|
|
|
sd_transfer_error:
|
|
panicf("transfer error : %d",ret);
|
|
card_info.initialized = 0;
|
|
return ret;
|
|
}
|
|
|
|
int sd_read_sectors(unsigned long start, int count, void* buf)
|
|
{
|
|
return sd_transfer_sectors(start, count, buf, false);
|
|
}
|
|
|
|
int sd_write_sectors(unsigned long start, int count, const void* buf)
|
|
{
|
|
#if 1 /* disabled until stable*/ \
|
|
|| defined(BOOTLOADER) /* we don't need write support in bootloader */
|
|
(void) start;
|
|
(void) count;
|
|
(void) buf;
|
|
return -1;
|
|
#else
|
|
return sd_transfer_sectors(start, count, (void*)buf, true);
|
|
#endif
|
|
}
|
|
|
|
#ifndef BOOTLOADER
|
|
long sd_last_disk_activity(void)
|
|
{
|
|
return last_disk_activity;
|
|
}
|
|
|
|
void sd_enable(bool on)
|
|
{
|
|
/* TODO */
|
|
(void)on;
|
|
return;
|
|
}
|
|
|
|
tCardInfo *card_get_info_target(int card_no)
|
|
{
|
|
(void)card_no;
|
|
return &card_info;
|
|
}
|
|
|
|
#endif /* BOOTLOADER */
|