Drop most of the cases: only keep 64 MHz and 133 MHz. Pick values
from the manual which seem to match real life values.
Change-Id: I912752fbe372f9f44207db6853d0ff92fd619bed
On the ZEN X-Fi2, the fractiona dividers are gated by the
bootloader and must be ungated before switching emi to pll.
Change-Id: I5df57ed5581054883da4cbb3b4f3ce3539391ab5
Currently don't do anything on stmp3600 because emi is completely
different. On stmp3700 it is unsure how the pll lock is handled
and this will need more testing.
Change-Id: I3d11282531f54f2ecc4187c0d913e2c61f4de14d
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.
Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
