imx233: rework emi frequency scaling
Drop most of the cases: only keep 64 MHz and 133 MHz. Pick values from the manual which seem to match real life values. Change-Id: I912752fbe372f9f44207db6853d0ff92fd619bed
This commit is contained in:
Amaury Pouly
parent
142ce48771
commit
fb35f06bf5
1 changed files with 48 additions and 57 deletions
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@ -28,62 +28,48 @@ struct emi_reg_t
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uint32_t value;
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};
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/* hardcode all the register values for the different settings. This is ugly
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* but I don't understand what they mean and it's faster this way so...
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* Recall that everything should be put in iram !
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/* hardcode all the register values for the different settings. This avoid
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* computing the register values at runtime since they never change and also
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* avoid wasting some space in iram.
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* Values from IMX233 manual, for Mobile DDR 7.5ns (133 MHz and 64MHz)
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* Make sure the last value is written to register 40. */
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/* Values extracted from Sigmatel linux port (GPL) */
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/** mDDR value */
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static struct emi_reg_t settings_24M[15] ICONST_ATTR =
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{
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{4, 0x01000101}, {7, 0x01000101}, {12, 0x02010002}, {13, 0x06060a02},
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{15, 0x01030000}, {17, 0x2d000102}, {18, 0x20200000}, {19, 0x027f1414},
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{20, 0x01021608}, {21, 0x00000002}, {26, 0x000000b3}, {32, 0x00030687},
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{33, 0x00000003}, {34, 0x000012c1}, {40, 0x00010000}
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};
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static struct emi_reg_t settings_48M[15] ICONST_ATTR =
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{
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{4, 0x01000101}, {7, 0x01000101}, {13, 0x06060a02}, {12, 0x02010002},
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{15, 0x02040000}, {17, 0x2d000104}, {18, 0x1f1f0000}, {19, 0x027f0a0a},
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{20, 0x01021608}, {21, 0x00000004}, {26, 0x0000016f}, {32, 0x00060d17},
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{33, 0x00000006}, {34, 0x00002582}, {40, 0x00020000}
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};
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static struct emi_reg_t settings_60M[15] ICONST_ATTR =
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{
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{4, 0x01000101}, {7, 0x01000101}, {12, 0x02020002}, {13, 0x06060a02},
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{15, 0x02040000}, {17, 0x2d000005}, {18, 0x1f1f0000}, {19, 0x027f0a0a},
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{20, 0x02040a10}, {21, 0x00000006}, {26, 0x000001cc}, {32, 0x00081060},
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{33, 0x00000008}, {34, 0x00002ee5}, {40, 0x00020000}
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};
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static struct emi_reg_t settings_80M[15] ICONST_ATTR __attribute__((alias("settings_60M")));
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static struct emi_reg_t settings_96M[15] ICONST_ATTR =
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{
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{4, 0x00000101}, {7, 0x01000001}, {12, 0x02020002}, {13, 0x06070a02},
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{15, 0x03050000}, {17, 0x2d000808}, {18, 0x1f1f0000}, {19, 0x020c1010},
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{20, 0x0305101c}, {21, 0x00000007}, {26, 0x000002e6}, {32, 0x000c1a3b},
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{33, 0x0000000c}, {34, 0x00004b0d}, {40, 0x00030000}
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};
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static struct emi_reg_t settings_120M[15] ICONST_ATTR =
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{
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{4, 0x00000101}, {7, 0x01000001}, {12, 0x02020002}, {13, 0x06070a02},
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{15, 0x03050000}, {17, 0x2300080a}, {18, 0x1f1f0000}, {19, 0x020c1010},
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{20, 0x0306101c}, {21, 0x00000009}, {26, 0x000003a1}, {32, 0x000f20ca},
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{33, 0x0000000f}, {34, 0x00005dca}, {40, 0x00040000}
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{4, 0x01000101}, /* DLL bypass mode, concurrent auto-precharge and bank split */
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{7, 0x01000101}, /* Read/write grouping, extra clock for back to back, priority placement */
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{12, 0x02020002}, /* tWR = 2 cycles, tRRD = 1 cycles, tCKE = 2 cycles */
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{13, 0x06060a02}, /* CAS lat gate = 3.0 cycles, CAS lat = 3.0 cycles, tWTR = 2 */
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{15, 0x02040000}, /* tRP = 2 cycles, tDAL = 4 cycles */
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{17, 0x2d000005}, /* DDL: start point = 45, lock = 0, increment = 0, tRC = 5 cycles */
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{18, 0x00000000}, /* */
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{19, 0x01000b0b}, /* DLL: DQS out shift (bypass) = 1, DQS delay bypass (1/0) = 11 / 11 */
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{20, 0x02030a00}, /* tRCD = 2 cycles, tRAS (min) = 3 cycles, DQS write shift (bypass) = 10 */
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{21, 0x00000005}, /* tRFC = 5 cycles */
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{26, 0x000001cc}, /* tREF = 460 cycles */
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{32, 0x00081060}, /* tRAS (max) = 4192 cycles, tXSNR = 8 cycles */
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{33, 0x00000008}, /* tXSR = 8 cycles */
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{34, 0x00002ee5}, /* tINIT = 12005 cycles */
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{40, 0x00020000} /* tPDEX = 2 */
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};
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static struct emi_reg_t settings_133M[15] ICONST_ATTR =
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{
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{4, 0x00000101}, {7, 0x01000001}, {12, 0x02020002}, {13, 0x06070a02},
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{15, 0x03050000}, {17, 0x2000080a}, {18, 0x1f1f0000}, {19, 0x020c1010},
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{20, 0x0306101c}, {21, 0x0000000a}, {26, 0x00000408}, {32, 0x0010245f},
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{33, 0x00000010}, {34, 0x00006808}, {40, 0x00040000}
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{4, 0x00000101}, /* concurrent auto-precharge and bank split */
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{7, 0x01000001}, /* Read/write grouping, priority placement */
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{12, 0x02020002}, /* tWR = 2 cycles, tRRD = 2 cycles, tCKE = 2 cycles */
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{13, 0x06070a02}, /* CAS lat gate = 3.0 cycles, CAS lat = 3.5 cycles, tWTR = 2 */
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{15, 0x03050000}, /* tRP = 3 cycles, tDAL = 5 cycles */
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{17, 0x19000f0a}, /* DDL: start point = 25, lock = 0, increment = 15, tRC = 10 cycles */
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{18, 0x1f1f0000}, /* DLL: DQS delay (1/0) = 31 / 31 */
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{19, 0x000a0000}, /* DLL: DQS out shift = 10 */
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{20, 0x03060023}, /* tRCD = 3 cycles, tRAS (min) = 6 cycles, DQS write shift = 35 */
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{21, 0x0000000a}, /* tRFC = 10 cycles */
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{26, 0x000003f7}, /* tREF = 1015 cycles */
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{32, 0x001023cd}, /* tRAS (max) = 9165 cycles, tXSNR = 16 cycles */
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{33, 0x00000010}, /* tXSR = 16 cycles */
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{34, 0x00006665}, /* tINIT = 26213 cycles */
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{40, 0x00040000} /* tPDEX = 4 */
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};
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static struct emi_reg_t settings_155M[15] ICONST_ATTR __attribute__((alias("settings_133M")));
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@ -148,7 +134,7 @@ void imx233_emi_set_frequency(unsigned long freq)
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* possible in this state anyway.
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* WARNING DANGER don't call any external function when sdram is disabled
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* otherwise you'll poke sdram and trigger a fatal data abort ! */
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/* first disable all interrupts */
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* flush the cache */
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@ -159,14 +145,19 @@ void imx233_emi_set_frequency(unsigned long freq)
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while(!BF_RD(EMI_STAT, DRAM_HALTED));
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/* load timings */
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struct emi_reg_t *regs;
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if(freq <= 24000) regs = settings_24M;
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else if(freq <= 48000) regs = settings_48M;
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else if(freq <= 60000) regs = settings_60M;
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else if(freq <= 80000) regs = settings_80M;
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else if(freq <= 96000) regs = settings_96M;
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else if(freq <= 120000) regs = settings_120M;
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else if(freq <= 133000) regs = settings_133M;
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else regs = settings_155M;
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switch(freq)
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{
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case IMX233_EMIFREQ_151_MHz:
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regs = settings_155M;
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break;
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case IMX233_EMIFREQ_130_MHz:
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regs = settings_133M;
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break;
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case IMX233_EMIFREQ_64_MHz:
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default:
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regs = settings_60M;
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break;
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}
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do
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HW_DRAM_CTLxx(regs->index) = regs->value;
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