imx233: rewrite emi using new register headers
Change-Id: Ie893162aac38ea3aaf73b4e84e54be714a5fc33f
This commit is contained in:
Amaury Pouly
parent
2a01b3766f
commit
e6a931301f
2 changed files with 17 additions and 230 deletions
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@ -129,10 +129,10 @@ void imx233_emi_set_frequency(unsigned long freq) ICODE_ATTR;
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void imx233_emi_set_frequency(unsigned long freq)
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{
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/** FIXME we rely on the compiler to NOT use the stack here because it's
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* in iram ! If it's not smart enough, one can switch the switch to use
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* not in iram ! If it's not smart enough, one can switch the switch to use
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* the irq stack since we are running interrupts disable here ! */
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/** BUG for freq<=24 MHz we must keep bypass mode since we run on xtal
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* we this setting is unused by our code so ignore this bug for now */
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* since this setting is unused by our code so ignore this bug for now */
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/** WARNING DANGER
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* Changing the EMI frequency is complicated because it requires to
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* completely shutdown the external memory interface. We must make sure
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@ -140,17 +140,19 @@ void imx233_emi_set_frequency(unsigned long freq)
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* the sdram will be made during the change. Care must be taken w.r.t to
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* the cache also. */
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/** FIXME assume that auto-slow is disabled here since that could put some
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* clock below the minimum value and we want to spend as less time as
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* possible in this state anyway. */
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* clock below the minimum value and we want to spend as least time as
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* possible in this state anyway.
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* WARNING DANGER don't call any external function when sdram is disabled
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* otherwise you'll poke sdram and trigger a fatal data abort ! */
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/* first disable all interrupts */
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int oldstatus = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* flush the cache */
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commit_discard_idcache();
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/* put DRAM into self-refresh mode */
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HW_DRAM_CTL08 |= HW_DRAM_CTL08__SREFRESH;
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HW_DRAM_CTL08 |= BM_DRAM_CTL08_SREFRESH;
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/* wait for DRAM to be halted */
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while(!(HW_EMI_STAT & HW_EMI_STAT__DRAM_HALTED));
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while(!BF_RD(EMI_STAT, DRAM_HALTED));
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/* load timings */
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struct emi_reg_t *regs;
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if(freq <= 24000) regs = settings_24M;
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@ -170,7 +172,7 @@ void imx233_emi_set_frequency(unsigned long freq)
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/* wait for transition */
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while(BF_RD(CLKCTRL_EMI, BUSY_REF_XTAL));
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/* put emi dll into reset mode */
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__REG_SET(HW_EMI_CTRL) = HW_EMI_CTRL__DLL_RESET | HW_EMI_CTRL__DLL_SHIFT_RESET;
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HW_EMI_CTRL_SET = BM_EMI_CTRL_DLL_RESET | BM_EMI_CTRL_DLL_SHIFT_RESET;
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/* load the new frequency dividers */
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set_frequency(freq);
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/* switch emi back to pll */
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@ -178,13 +180,13 @@ void imx233_emi_set_frequency(unsigned long freq)
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/* wait for transition */
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while(BF_RD(CLKCTRL_EMI, BUSY_REF_EMI));
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/* allow emi dll to lock again */
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__REG_CLR(HW_EMI_CTRL) = HW_EMI_CTRL__DLL_RESET | HW_EMI_CTRL__DLL_SHIFT_RESET;
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HW_EMI_CTRL_CLR = BM_EMI_CTRL_DLL_RESET | BM_EMI_CTRL_DLL_SHIFT_RESET;
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/* wait for lock */
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while(!(HW_DRAM_CTL04 & HW_DRAM_CTL04__DLLLOCKREG));
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while(!BF_RD(DRAM_CTL04, DLLLOCKREG));
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/* get DRAM out of self-refresh mode */
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HW_DRAM_CTL08 &= ~HW_DRAM_CTL08__SREFRESH;
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HW_DRAM_CTL08 &= ~BM_DRAM_CTL08_SREFRESH;
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/* wait for DRAM to be to run again */
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while(HW_EMI_STAT & HW_EMI_STAT__DRAM_HALTED);
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while(HW_EMI_STAT & BM_EMI_STAT_DRAM_HALTED);
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restore_interrupt(oldstatus);
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}
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@ -25,225 +25,10 @@
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#include "system.h"
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#include "system-target.h"
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#define HW_EMI_BASE 0x80020000
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#include "regs/regs-emi.h"
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#include "regs/regs-dram.h"
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#define HW_EMI_CTRL (*(volatile uint32_t *)(HW_EMI_BASE + 0x0))
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#define HW_EMI_CTRL__DLL_SHIFT_RESET (1 << 25)
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#define HW_EMI_CTRL__DLL_RESET (1 << 24)
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/* this register is undocumented but exists, I put the whole doc here */
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#define HW_EMI_STAT (*(volatile uint32_t *)(HW_EMI_BASE + 0x10))
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#define HW_EMI_STAT__DRAM_PRESENT (1 << 31)
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#define HW_EMI_STAT__NOR_PRESENT (1 << 30)
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#define HW_EMI_STAT__LARGE_DRAM_ENABLED (1 << 29)
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#define HW_EMI_STAT__DRAM_HALTED (1 << 1)
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#define HW_EMI_STAT__NOR_BUSY (1 << 0)
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/* another undocumented registers (there are some more) */
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#define HW_EMI_TIME (*(volatile uint32_t *)(HW_EMI_BASE + 0x20))
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#define HW_EMI_TIME__THZ_BP 24
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#define HW_EMI_TIME__THZ_BM (0xf << 24)
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#define HW_EMI_TIME__TDH_BP 16
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#define HW_EMI_TIME__TDH_BM (0xf << 16)
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#define HW_EMI_TIME__TDS_BP 8
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#define HW_EMI_TIME__TDS_BM (0x1f << 8)
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#define HW_EMI_TIME__TAS_BP 0
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#define HW_EMI_TIME__TAS_BM (0xf << 0)
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/** WARNING: the HW_DRAM_* registers don't have a SCT variant ! */
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#define HW_DRAM_BASE 0x800E0000
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#define HW_DRAM_CTLxx(xx) (*(volatile uint32_t *)(HW_DRAM_BASE + 0x4 * (xx)))
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#define HW_DRAM_CTL00 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x0))
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#define HW_DRAM_CTL01 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x4))
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#define HW_DRAM_CTL02 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x8))
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#define HW_DRAM_CTL03 (*(volatile uint32_t *)(HW_DRAM_BASE + 0xc))
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#define HW_DRAM_CTL04 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x10))
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#define HW_DRAM_CTL04__DLL_BYPASS_MODE (1 << 24)
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#define HW_DRAM_CTL04__DLLLOCKREG (1 << 16)
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#define HW_DRAM_CTL05 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x14))
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#define HW_DRAM_CTL05__EN_LOWPOWER_MODE (1 << 0)
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#define HW_DRAM_CTL06 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x18))
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#define HW_DRAM_CTL07 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x1c))
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#define HW_DRAM_CTL08 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x20))
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#define HW_DRAM_CTL08__SREFRESH (1 << 8)
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#define HW_DRAM_CTL09 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x24))
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#define HW_DRAM_CTL10 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x28))
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#define HW_DRAM_CTL10__TEMRS_BP 8
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#define HW_DRAM_CTL10__TEMRS_BM (0x3 << 8)
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#define HW_DRAM_CTL11 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x2c))
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#define HW_DRAM_CTL11__CASLAT_BP 0
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#define HW_DRAM_CTL11__CASLAT_BM (0x7 << 0)
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#define HW_DRAM_CTL12 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x30))
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#define HW_DRAM_CTL12__TCKE_BP 0
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#define HW_DRAM_CTL12__TCKE_BM (0x7 << 0)
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#define HW_DRAM_CTL12__TRRD_BP 16
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#define HW_DRAM_CTL12__TRRD_BM (0x7 << 16)
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#define HW_DRAM_CTL12__TWR_INT_BP 24
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#define HW_DRAM_CTL12__TWR_INT_BM (0x7 << 24)
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#define HW_DRAM_CTL13 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x34))
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#define HW_DRAM_CTL13__TWTR_BP 0
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#define HW_DRAM_CTL13__TWTR_BM (0x7 << 0)
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#define HW_DRAM_CTL13__CASLAT_LIN_BP 16
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#define HW_DRAM_CTL13__CASLAT_LIN_BM (0xf << 16)
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#define HW_DRAM_CTL13__CASLAT_LIN_GATE_BP 24
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#define HW_DRAM_CTL13__CASLAT_LIN_GATE_BM (0xf << 24)
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#define HW_DRAM_CTL14 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x38))
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#define HW_DRAM_CTL15 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x3c))
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#define HW_DRAM_CTL15__TDAL_BP 16
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#define HW_DRAM_CTL15__TDAL_BM (0xf << 16)
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#define HW_DRAM_CTL15__TRP_BP 24
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#define HW_DRAM_CTL15__TRP_BM (0xf << 24)
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#define HW_DRAM_CTL16 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x40))
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#define HW_DRAM_CTL16__TMRD_BP 24
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#define HW_DRAM_CTL16__TMRD_BM (0x1f << 24)
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#define HW_DRAM_CTL17 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x44))
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#define HW_DRAM_CTL17__TRC_BP 0
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#define HW_DRAM_CTL17__TRC_BM (0x1f << 0)
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#define HW_DRAM_CTL17__DLL_INCREMENT_BP 8
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#define HW_DRAM_CTL17__DLL_INCREMENT_BM (0xff << 0)
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#define HW_DRAM_CTL17__DLL_START_POINT_BP 24
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#define HW_DRAM_CTL17__DLL_START_POINT_BM (0xff << 24)
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#define HW_DRAM_CTL18 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x48))
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#define HW_DRAM_CTL17__DLL_DQS_DELAY_0_BP 16
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#define HW_DRAM_CTL17__DLL_DQS_DELAY_0_BM (0x7f << 16)
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#define HW_DRAM_CTL17__DLL_DQS_DELAY_1_BP 24
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#define HW_DRAM_CTL17__DLL_DQS_DELAY_1_BM (0x7f << 24)
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#define HW_DRAM_CTL19 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x4c))
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#define HW_DRAM_CTL19__DQS_OUT_SHIFT_BP 16
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#define HW_DRAM_CTL19__DQS_OUT_SHIFT_BM (0x7f << 16)
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#define HW_DRAM_CTL20 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x50))
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#define HW_DRAM_CTL20__WR_DQS_SHIFT_BP 0
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#define HW_DRAM_CTL20__WR_DQS_SHIFT_BM (0x7f << 0)
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#define HW_DRAM_CTL20__TRAS_MIN_BP 16
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#define HW_DRAM_CTL20__TRAS_MIN_BM (0xff << 16)
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#define HW_DRAM_CTL20__TRCD_INT_BP 24
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#define HW_DRAM_CTL20__TRCD_INT_BM (0xff << 24)
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#define HW_DRAM_CTL21 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x54))
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#define HW_DRAM_CTL21__TRFC_BP 0
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#define HW_DRAM_CTL21__TRFC_BM (0xff << 0)
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#define HW_DRAM_CTL22 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x58))
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#define HW_DRAM_CTL23 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x5c))
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#define HW_DRAM_CTL24 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x60))
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#define HW_DRAM_CTL25 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x64))
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#define HW_DRAM_CTL26 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x68))
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#define HW_DRAM_CTL26__TREF_BP 0
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#define HW_DRAM_CTL26__TREF_BM (0xfff << 0)
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#define HW_DRAM_CTL27 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x6c))
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#define HW_DRAM_CTL28 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x70))
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#define HW_DRAM_CTL29 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x74))
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#define HW_DRAM_CTL30 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x78))
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#define HW_DRAM_CTL31 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x7c))
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#define HW_DRAM_CTL31__TDLL_BP 16
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#define HW_DRAM_CTL31__TDLL_BM (0xffff << 16)
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#define HW_DRAM_CTL32 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x80))
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#define HW_DRAM_CTL32__TRAS_MAX_BP 0
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#define HW_DRAM_CTL32__TRAS_MAX_BM (0xffff << 0)
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#define HW_DRAM_CTL32__TXSNR_BP 16
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#define HW_DRAM_CTL32__TXSNR_BM (0xffff << 16)
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#define HW_DRAM_CTL33 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x84))
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#define HW_DRAM_CTL33__TXSR_BP 0
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#define HW_DRAM_CTL33__TXSR_BM (0xffff << 0)
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#define HW_DRAM_CTL34 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x88))
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#define HW_DRAM_CTL34__TINIT_BP 0
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#define HW_DRAM_CTL34__TINIT_BM 0xffffff
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#define HW_DRAM_CTL35 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x8c))
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#define HW_DRAM_CTL36 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x90))
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#define HW_DRAM_CTL37 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x94))
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#define HW_DRAM_CTL38 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x98))
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#define HW_DRAM_CTL39 (*(volatile uint32_t *)(HW_DRAM_BASE + 0x9a))
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#define HW_DRAM_CTL40 (*(volatile uint32_t *)(HW_DRAM_BASE + 0xa0))
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#define HW_DRAM_CTL40__TPDEX_BP 16
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#define HW_DRAM_CTL40__TPDEX_BM (0xffff << 16)
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/** Interesting fields:
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* - TCKE: CTL12
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* - TDAL: CTL15
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* - TDLL: CTL31
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* - TEMRS: CTL10
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* - TINIT: CTL34
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* - TMRD: CTL16
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* - TPDEX: CTL40
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* - TRAS_MAX: CTL32
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* - TRAS_MIN: CTL20
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* - TRC: CTL17
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* - TRCD_INT: CTL20
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* - TREF: CTL26
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* - TRFC: CTL21
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* - TRP: CTL15
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* - TRRD: CTL12
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* - TWR_INT: CTL12
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* - TWTR: CTL13
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* - TXSNR: CTL32
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* - TXSR: CTL33
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* - DLL_DQS_DELAY_BYPASS_0
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* - DLL_DQS_DELAY_BYPASS_1
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* - DQS_OUT_SHIFT_BYPASS
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* - WR_DQS_SHIFT_BYPASS
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* - DLL_INCREMENT: CTL17
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* - DLL_START_POINT: CTL17
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* - DLL_DQS_DELAY_0: CTL18
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* - DLL_DQS_DELAY_1: CTL18
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* - DQS_OUT_SHIFT: CTL19
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* - WR_DQS_SHIFT: CTL20
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* - CAS: CTL11
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* - DLL_BYPASS_MODE: CTL04
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* - SREFRESH: CTL08
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* - CASLAT_LIN: CTL13
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* - CASLAT_LIN_GATE: CTL13
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*
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* Interesting registers:
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* - CTL04: DLL_BYPASS_MODE
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* - CTL08: SREFRESH
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* - CTL10: TEMRS
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* - CTL11: CASLAT
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* - CTL12: TCKE TRRD TWR_INT
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* - CTL13: TWTR CASLAT_LIN CASLAT_LIN_GATE
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* - CTL15: TDAL TRP
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* - CTL16: TMRD
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* - CTL17: TRC DLL_INCREMENT DLL_START_POINT
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* - CTL18: DLL_DQS_DELAY_0 DLL_DQS_DELAY_1
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* - CTL19: DQS_OUT_SHIFT
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* - CTL20: WR_DQS_SHIFT TRAS_MIN TRCD_INT
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* - CTL21 TRFC
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* - CTL26: TREF
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* - CTL31: TDLL
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* - CTL32: TRAS_MAX TXSNR TXSR: CTL33
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* - CTL34: TINIT
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* - CTL40: TPDEX
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* - DLL_DQS_DELAY_BYPASS_0
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* - DLL_DQS_DELAY_BYPASS_1
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* - DQS_OUT_SHIFT_BYPASS
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* - WR_DQS_SHIFT_BYPASS
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*/
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#define HW_DRAM_CTLxx(xx) (*(&HW_DRAM_CTL00 + (xx)))
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/**
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* Absolute maximum EMI speed: 151.58 MHz (mDDR), 130.91 MHz (DDR)
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