Although everything is implemented, recording still doesn't work,
dma is stuck. Add code for reference until this get a proper fix.
Change-Id: Ifc016b00876230c6d337a5cd4f8bb90b856efac8
The old driver didn't behave nicely because it waiting for
stability which could never arrive on some gestures. The new one
uses a fixed delay and averaging.
Change-Id: I8ff80f373b6792e6d5fc3cfe41b709642e61c38b
The lcd data line were not setup as input anymore, making register
reading plain broken and probably lead to bad lcd detection.
Change-Id: I281460f845537c58045f3893261ded5c9c6e53b5
Power management is somewhat different on stmp3700 which doesn't
have the 4.2V rail and completely different on stmp3600 which has
several DCDC. Currently only handle imx233.
Change-Id: Ic7815141286117b74022ffc53cfa48664fd7faac
Using the ssp macros, we can easily handle the stmp3600 which
has a single ssp block. Take care of all the nasty differences
between targets like bus width
Change-Id: If98a091cc262e9e6834f6fb9826f7c5515bfe621
Currently don't do anything on stmp3600 because emi is completely
different. On stmp3700 it is unsure how the pll lock is handled
and this will need more testing.
Change-Id: I3d11282531f54f2ecc4187c0d913e2c61f4de14d
Add finer granularity to start command: now commands can be
prepared, schedule and semaphore increased independently.
Change-Id: Ib1ed1f20f4b46dc61b6dbab6ddec8b54e3d832b9
Factorise pin setup, rewrite PIO code, add support for lcdif irq,
handle all the various differences between the stmps, drop yuv
blitting code since it already exists in the common lcd drivers.
Change-Id: Ifc40aed9b3b12f16611ce960602e46a5bc87ae53
The lradc architecture of the stmp3600 is rather different:
only channels 6 and 7 have configurable source and we need to
take care when allocating channels so that we can actually
measure the right channel! Delegate die temperature sensing to
the power block on stmp3600.
Change-Id: I0860eb4ea98240facc3d4a19d61684eca5f630cc
There are many small differences between them. In particular
some regulators are not available on stmp3600. Also the vbusvalid
detect method is not available as an irq on stmp3600 and seems
broken on stmp3700. Finally die temperature is handled by the
power block on stmp3600.
Change-Id: I2c68b418738f15564e445d3a1496018cef97fff7
Under some circumstance (timeout), the dma interrupt is not fired
and only the error one is. This can happen with some picky SD
cards and with the current code it causes a 1 second timeout.
This code properly catches the error interrupt to stop as soon
as possible.
Change-Id: I9c53ea272d01793f0f229571502e99eb62f1b723
The current pwm interface is too low-level. Introduce a higher
level setup function which directly computes the parameters from
the required frequency.
Change-Id: Ie95c7522e9f42492fe872203f4cab46770a9649a
The clkctrl functions were becoming a mess. Normalise the names,
get rid of the xtal derived as special case and use the same
interface.
Change-Id: Ib954a8d30a6bd691914b5e0d97774ec9fc560c50
A number of pins on the imx233 are standard and manually calling
functions to acquire, set function/drive/output is painful. This
will become unmanageable when we will add support for the other
stmp chips.
Introduce the concept of virtual pin which is a way to completely
describe a virtual pin (virtual because pins are muxed).
Change-Id: I01b6e040945648e58e1d1abab06529c9571c5f10
The current pinctrl functions were a mess. Normalise the functions
names to make them shorter and clearer.
Change-Id: Iac6ff84625ef2b7610268e3a5802dc0088de3167
The SD SWITCH command has a result and can take a long time to
finish. Ignoring the answer and waiting an arbitrary time is
unreliable at best.
Change-Id: I1bfbb193952b96598f8bb056bac88220d4edf1fc
Register set selection is based on the value of the
IMX233_SUBTARGET value. The reg-select.h file (used by the
generated headers), does the selection based on this value as
follows:
- 3600 <= . < 3700: stmp3600 register set
- 3700 <= . < 3780: stmp3700 register set
- 3780 <= .: imx233 register set
Note that this selector relies on the name of the socs in the
register description to be respectively stmp3600, stmp3700 and
imx233.
Change-Id: I793b18e6c4f3fea85aa74f4c6be3affb0622c14e
This causes data_abort_handler from lib/unwarminder/safe_read.S to be
used instead. It allows unwarminder to avoid data aborts when
displaying the backtrace. A data_abort_handler remains in system-arm.c,
but it is not used because it is declared as a weak symbol.
Change-Id: I832066ed514347fe697e219872e90fbdd937f477
Reviewed-on: http://gerrit.rockbox.org/475
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
Tested-by: Boris Gjenero <boris.gjenero@gmail.com>
Split the ISR into two parts and alllow quick return from first half.
Introduces a uevent() API to have a callback happen in a specified
number of microseconds. Right now only one event is supported.
Change-Id: Ib1666165be2f6082e5275d64961f083cab104f9f
This speeds up partial updates quite a bit but what is more
important it opens up a way to efficiently implement
lcd_blit_yuv() using hw colorspace conversion.
Tested on rk27generic, hm60x v1 and v2 and on ma9.
Benchmark for hm60x v1 (by mortalis):
HEAD patched
1/1 141fps 138fps
1/4 315fps 395fps
Change-Id: I4cc115786c3139000fc14c49a7290e289cfd6c42
HAVE_SW_VOLUME_CONTROL is required and at this time only affects the
SDL targets using pcm-sdl.c.
Enables balance control in SDL targets, unless mono volume is in use.
Compiles software volume control as unbuffered when
PCM_SW_VOLUME_UNBUFFERED is defined. This avoids the overhead and
extra latency introduced by the double buffer when it is not needed.
Use this config when the target's PCM driver is buffered and sufficient
latency exists to perform safely the volume scaling.
Simulated targets that are double-buffered when made as native targets
remain so in the sim in order to run the same code.
Change-Id: Ifa77d2d3ae7376c65afecdfc785a084478cb5ffb
Reviewed-on: http://gerrit.rockbox.org/457
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested-by: Michael Sevakis <jethead71@rockbox.org>
Based on FS#9920 by Ryan Press with changes to selection logic so
that it works on my iPod Photo. Should also work on iPod Color/4G
and Mini2G. Moved all target specific code from
firmware/drivers/serial.c into new file
firmware/target/arm/pp/uart-pp.c in the same manner as other
target specific uart code.
Update to fix build error on ipodmini2g by adding defines in config file.
Removed unwanted whitespace
Tested on iPod Photo.
Change-Id: Ia5539563966198e06372d70b5adf2ef78882f863
Reviewed-on: http://gerrit.rockbox.org/455
Reviewed-by: andypotter <liveboxandy@gmail.com>
Tested-by: andypotter <liveboxandy@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
* SOUND_x enum can be generated by audiohw_settings.h along with settings
entries and sound_val2phys.
* VOLUME_MIN and VOLUME_MAX are no longer necessary within sound.c. If
you need them, they are for target-defined purposes.
* Fix up SDL volume implementation in sdl.c. Move sim volume calculation
code to pcm-sdl.c.
* Min trigger tresholds were based upon VOLUME_MIN for some reason.
These setting have nothing to do with playback volume. Since it is no
longer present, set these at -89dB which is the minimum peak meter
sensitivity setting.
* Fix an oversight in wm8758.c. I forgot to add the dB->register
conversion to audiohw_set_volume.
Change-Id: Ie1df33f1793eee75e6793f16bc7bddd16edb7f75
This is going right in since it's long overdue. If anything is goofed,
drop me a line or just tweak it yourself if you know what's wrong. :-)
Make HW/SW codec interface more uniform when emulating HW functionality
on SWCODEC for functions such as "audiohw_set_pitch". The firmware-to-
DSP plumbing is in firmware/drivers/audiohw-swcodec.c. "sound_XXX"
APIs are all in sound.c with none in DSP code any longer.
Reduce number of settings definitions needed by each codec by providing
defaults for common ones like balance, channels and SW tone controls.
Remove need for separate SIM code and tables and add virtual codec header
for hosted targets.
Change-Id: I3f23702bca054fc9bda40f49824ce681bb7f777b
Onda VX747 sim was missing a limits #define; #include limits.h in
pcm_sw_volume.h.
Simply use the software volume control for the SIM volume control
rather than the SDL volume control when the target would have it
natively.
Change-Id: I8e924a2ff1b410f602452d2ea9b691efb82c931e
Implements double-buffered volume, balance and prescaling control in
the main PCM driver when HAVE_SW_VOLUME_CONTROL is defined ensuring
that all PCM is volume controlled and level changes are low in latency.
Supports -73 to +6 dB using a 15-bit factor so that no large-integer
math is needed.
Low-level hardware drivers do not have to implement it themselves but
parameters can be changed (currently defined in pcm-internal.h) to work
best with a particular SoC or to provide different volume ranges.
Volume and prescale calls should be made in the codec driver. It should
appear as a normal hardware interface. PCM volume calls expect .1 dB
units.
Change-Id: Idf6316a64ef4fb8abcede10707e1e6c6d01d57db
Reviewed-on: http://gerrit.rockbox.org/423
Reviewed-by: Michael Sevakis <jethead71@rockbox.org>
Tested-by: Michael Sevakis <jethead71@rockbox.org>
The old way actually mis-used the API (I misunderstood the docs) because
it specified the marker position as a "low buffer watermark" but instead of a
future playback head position.
The replacement is a simple thread that writes the data regardless of the
filling level of the buffer (write() will just block) and polls the playback
state periodically.
Change-Id: If29237cee4ce78dc42f5a8320878bab0cafe78f7
Reviewed-on: http://gerrit.rockbox.org/422
Tested-by: Dominik Riebeling <Dominik.Riebeling@gmail.com>
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
This was spotted while playing with qemu-jz:
1) rockbox reads TECR and TESR which are described as write-only
registers. Datasheet doesn't mention what happens if they are
readed. Apparently this doesn't have fatal side effects.
It comes down to two defines from jz4740.h
__tcu_stop_counter(n) and __tcu_start_counter(n) which use
read-modify-write sequence.
2) rockbox accesses out of bound offset 0xd4 in DMA memspace.
It comes from dis_irq() in system-jz4740.c. NUM_DMA is 6 but
DMA channels are 0-5 so (irq <= IRQ_DMA_0 + NUM_DMA)) bound
check is wrong.
This are *NOT* tested on device.
Change-Id: I29dff6a4f828030877b7d50fbcc98866478b9e3d
Reviewed-on: http://gerrit.rockbox.org/338
Reviewed-by: Bertrik Sikken <bertrik@sikken.nl>
Tested-by: Purling Nayuki <cyq.yzfl@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
This patch adds to YP-R0 (and other future targets using Linux
framebuffer) the ability to use LCD_ENABLE to save some CPU cycles
while display is powered off.
This patch also changes the way to toggle LCD power: now using
a proper ioctl call, slightly more efficient.
Change-Id: I544de77f5abd4ac1c13d3fe3a6e40a30f7c0bece
Reviewed-on: http://gerrit.rockbox.org/410
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
The GPIO device file wasn't closed due to this. This wasn't a big deal
because the device powers off shorty afterwards anyway.
Change-Id: I9a6b4d57d32627157323b4883e47b8812f5dcb4d
As per title this patch aims at splitting common target
code and specific target code in a better way to
support future ports within the same environment
(e.g. Samsung YP-R1 where the Linux and the SoC
are the same, with differences in hardware devices
handling)
Change-Id: I67b4918c46403b184d3d8f42ab5aae7d01037fd0
Reviewed-on: http://gerrit.rockbox.org/409
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
commit_discard_dcache_range() is used in sd, lcd and pcm drivers
to handle transfers form/to data buffers so this should not introduce
any problems. It is reported to fix pop noise observed on some hifimans.
We apparently don't fully understand cache handling on this platform.
Change-Id: I436d291509f91d16a13d10965a28171fb27574ab
In commit_discard_idcache(), cache lines were marked as invalid. When
some cache lines are marked as invalid, memory corruption can occur.
This caused instability when using PP502x ATA DMA because of the many
more calls to that function. Here, commit_discard_idcache() is changed
to avoid the problem. Also, the cache is filled after being enabled to
to ensure there are never any cache lines that aren't marked as valid.
Change-Id: Ia26300acef6b0573c1f40299c496ee5cbda3dac8
Reviewed-on: http://gerrit.rockbox.org/339
Reviewed-by: Szymon Dziok <b0hoon@o2.pl>
Tested-by: Szymon Dziok <b0hoon@o2.pl>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
The SD driver doesn't initialised drives at the beginning but
upon request to handle removable drives. Since means that the
init should call init_drive() and not init_sd_card() otherwise
the check for WINDOW flag is bypasses. This breaks the zenxfi3
bootloader and has been overlooked for some time.
Change-Id: I7325f7164d16d7e7e54eeb4645e98517a08e0836
Move to a table based approach (scales better) and distinguish
between upward changes (increase frequency) and downward changes
(decrease frequency). This provides a better ordering of
operations and in particular it allows to avoid changing the
regulator while running at low speed since it takes a long time !
This should result in a much smoother scaling.
Change-Id: Iad7e5b61277e215f31c07877fbbad07ddde1171f
For some reason it is the responsability of the driver to send
this event so do it. This might fix some non-updating screens.
Change-Id: Ib5fdc94bf266c3497a8ac4e89d0418c0e876ff9f
The lcd kind is always set to st7783 in case we can't read the ID
so don't bother handling impossible cases
Change-Id: I352fd43b26068b460e69190d37c4cd4627e1db9a
The flip and invert settings can potentially be reset to their
value accross a disable/enable cycle, so save the value of the
impacted registers and apply it after each enable. Also avoid
poking registers when the lcd is not on.
Change-Id: Ica98f166c060aade7eb205f5628b58aae692024f
When chaging the cpu and memory frequency we need to disable the
external memory interface (EMI) for a small time. This can
underflow the dma and cause some breakage. Hopefully the SSP
controller handles this gracefully by stopping the clock and the
I2C probably handles this naturally because the clock can be
streched anyway. However the LCDIF has a special setting for this
which needs to be enable, otherwise it will send garbage to the
LCD. No other block is known to suffer from this currently but
this issue might have more unexpected consequences.
Change-Id: Ide154cad87929f2bf6cc419ac1d2ff33e30eec66
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.
Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
pcm_dma_apply_settings(): sets the configured PCM frequency,
all native CS42L55 sample rates are available.
Change-Id: I2fcd5581457a669c3044516804cb64fb972218d0
Actually Rockbox does not use this mode, it is supported by
other iPods, so implemented on Classic as well.
Change-Id: Ia6578506df27a95a7f7522b3034b764631a8bb3a
Scale battery voltage ADC readings by 1023 instead of 1000,
using ADC1 (substractor) instead of ADC0 (multiplicator) to
get better resolution.
Percent charge/discharge tables are also modified to return
a similar value than the old ones.
Change-Id: I2951c75faa02f4302599ec24f9156cfd209c36eb
On heavy storage operations (like database update), the ssp dma
irq can be fired around ~10000/sec.
Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
Do low level power init in system_init(). This can be needed
since imx233 must be able to frequecy scale atfer system_init()
and kernel_init() and this is only possible if power system was
initialised.
Change-Id: I27c66ec0dccd60bda26a45be24683c0bfe72c6da
The current code uses the msec irq to collect statistics and
detect irq storms (debug). But this irq is triggered 1000 times
per sec and we don't need that accuracy. This commit removes the
msec irq and use the tick timer instead which is triggered only
100 times per second.
Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
The lcd driver does not wait for the refresh to be done to return
from lcd_update(). This means that changing a register is unsafe
if done in the middle of the redraw. This could happen when
disabling the lcd for example. Make sure it doesn't happen by
waiting for the lcdif to be ready.
Change-Id: I43ec62a637dd61c3b2a3a6e131c1a9e8035524b1
When changing the cpu frequency, it is important to make sure that
HBUS stays at a reasonable frequency otherwise the chip will
crash. Special care is needed about auto-slow and clk_p/clk_h
ratio on intermediate steps.
Change-Id: Ief9f68ddf286caabe75c879718dac5027ab1560f
Make sure DCDC is running at boot (it is disabled by default when
5V is present and we don't want to rely on the bootloader to
change this).
When changing the voltage on a regulator, it usually takes 2ms for
the voltage to stabilize. In DCDC mode, there is an irq to notify
about the event so use it ! This is especially important when
changing cpu frequency because increasing the cpu freq while the
voltage is rising is unreliable.
Change-Id: Icfe9ef3ee90156d1e17da0820d9041859f7f3bca
HBUS uses the same field for integer and fractional dividers, the
choice is made by a bit. Make sure both are changed together,
otherwise this could result in the wrong divider to be used and in
HBUS freq to be too low or too high (very bad).
Change-Id: I253d8eeee26c5038868b729c4f791511295a39f0
Ideally someone will go through and make a graphic for the 6G, but as it looks nearly identical to the Video its not a huge deal.
Change-Id: If507c6d4f01eb0b1e5fc2f15f6a0e5a3195006c6
Uninitialized struct scroll which is used to pass state between
scrollstrip ISR and button_read_device() can bomb out whole
button subsytem.
Change-Id: I3b415c22cfee4181b2132cddaeff68797c7cc0ea
If interrupts trigger during cache invalidation this could cause memory
corruption. This should be right fix for commit_discard_idcache in
contrast to 72ebcbf and c1ec1ec.
Change-Id: I141fb585004d4a1967b0a03bc37db3964d886564
Reviewed-on: http://gerrit.rockbox.org/345
Tested-by: Andrew Ryabinin <ryabinin.a.a@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
It seems something wrong with cache handling in rk27xx. OF always disable cache
before invalidating cache ways, therefore, now we do the same.
Hopefully this will fix cache handling, but I couldn't contend that it's really so.
Change-Id: I967c18211f0ddff689b6a17579fbe8685277f132
This is work from FS#12431 synced to current HEAD and slightly
tweaked (gcc 4.6.2 -> 4.6.3, binutils 2.21.1 -> 2.22)
Change-Id: I76af91e80ac2a9c16a776c7f0a33cc51603bbf9b
The running count is only 16-bit wide, since the always tick
setting derives from the crystal clock at 24MHz the user timer
cannot be set lower than ~300Hz which is already too high.
Switch to the 32KHz crystal source to fix this.
Change-Id: Ie7775460b17ea7ab331738734e3d688ad5563857
Several HM-801 DAPs have another buttons circuit.
This patch adds support for such devices so they could work properly.
Change-Id: Ic49e8e46b3e785b91c7c4706003fac3dbc20ae59
Uses register polling method to decide when it's time to decode
RDS packets.
Change-Id: I1d3cc995ea3350ec7b101438b8f2027130d4a4c9
Reviewed-on: http://gerrit.rockbox.org/320
Reviewed-by: Lorenzo Miori <memorys60@gmail.com>
Tested-by: Lorenzo Miori <memorys60@gmail.com>
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
We should cast to (volatile uint32_t*) here, because attempt to refer to volatile
object through use of an lvalue with non-volatile-qualified type will result in
undefined behavior.
Change-Id: I1b2e9688af11d3dcba518a5e31865d703b54b635
Use DMA engine for fullscreen updates and bypass mode for partial
updates. This gives major boost on rk27generic:
default ARM:AHB:APB 200💯50
HEAD 1/1: 26.3fps 1/4: 105.0fps
patched 1/1: 116.5fps 1/4: 249.5fps
with freq scalling NORMAL mode ARM:AHB:APB 50:50:50
HEAD 1/1: 13.1fps 1/4: 52.5fps
patched 1/1: 54.5fps 1/4: 119.0fps
Tested on rk27generic noname DAP and on Hifimans.
Change-Id: Id9dd4d2d61542c7ea6b5c6336b170d6357cefde9
This version resembles how OF handle cache invalidates.
This seems to fix mysterious data aborts on plugin/codec loading
after introducing frequency scaling.
Credit goes to mortalis for pinpointing the reason of aborts.
Change-Id: I3477b3f65d593d7b43c36a0b06d863f71f000812
The functions document my reverse engineer findings about nand
controller. This code is commented out and is purely for reference
as FTL scheme is still unknown.
Change-Id: I70edeb4bfb0cbd51b6adc15afa7193dd8f71e8da
Frequency scaling seems to be unstable and causes the device to
freeze. It is unclear why at the moment, perhaps we need to ramp
up the vddd voltage to avoid a false brownout ?
Change-Id: I7aaea9d7c213922a65250fe50775fb785d430226
