headphone ADC thread stack was slightly too small. Bump it up a bit.
(it was _perfectly_ sized for the prior older toolchain+optimization flags...)
Change-Id: I2ca67c2b85c54f879892a31e281d7696f893389c
Use of IF_COP_CORE was mistakenly introduced as part of 89acde6af2,
effectively short-circuiting multiple tests resulting in the code
paths always being executed, on both cores.
Use the correct macro, so per-CPU paths are handled properly.
Change-Id: Id346cf759fc1b06b7d56694d7af1f469caf785a4
This appears to finally fix the issue
turns out the status register we were writing was only for the CPU
COP cache flush wiped out the CPU cache
--
Added some defines to cut down on the magic numbers
Added some comments explaining such
Set the address to full 20 bit address
0x1FFFFF which is then left shifted 11 internally -- somewhere around 4GB?
Link explains the cache status bits
https://daniel.haxx.se/sansa/memory_controller.txt
Change-Id: I57b7187c2f71a5b54ce145bf3a21ed492a8993cb
Enable its use in the jz47xx MIPS targets.
(accidently committed g#3249 before making these changes)
Change-Id: I1791946f632901f0c7a94b04b009671aa0d71717
This is just a minor cleanup of Solomon Peachy's code, and using
per-filesystem buffers instead of a single static buffer.
Tested and working on the FiiO M3K.
Change-Id: I3c19e8cc24e2f8aa07668c9d1c6d63364815050a
This uses the new unicode string literal feature that is available
now to greatly simplify the initialization of these special string
types. This makes them much more readable at a quick glance.
Change-Id: Iad8b49aa763486608e3bb7e83fb8abfb48ce0a7b
-- apparenty 0x4 aligned doesn't work properly
requires 0x8 alignment at least for the h10 20gb
but enabled for all processors that define MEM_ALIGN_ATTR
Change-Id: I11edaab183b91a6d158f1f439f173b9b699dc914
-- apparenty 0x4 aligned doesn't work properly
requires 0x8 alignment at least for the h10 20gb
but enabled for all arm processors
assign the default framebuffer to the default_vp as well
Change-Id: I0b76c30f2ddb5d6d2f7c6a132e4081aee58da17b
In the old position of the call, the first battery reading would
be made before initializing the target's power management code.
If the target needs to initialize before giving a battery reading,
then the first reading would be wrong and the power thread might
inappropriately shut down based on a false zero reading.
The new position avoids forcing special-case logic onto the target
power management code.
Change-Id: I483cfabe30c6881d80a1094fd526fa0065523d19
This allows the user to make use of the DAC's power-saving abilities.
The two modes are "high performance" and "battery saver". This feature
is supported by the AK4376 DAC in the upcoming FiiO M3K port.
The setting is only a manual toggle right now, but in the future it
could be hooked up to the battery level (via another setting) so it
can be toggled automatically when the battery gets too low.
Change-Id: I482af6e2f969fcbdeb3411bd3ff91f866b12d027
The storage subsystem aggressively issues SLEEPNOW events when idle
and power off happened a fixed 2s later. This turns out to not be
enough time for FC1307A (eg iFlash) adapters to flush outstanding writes.
So, when we detect a lack of PM support, increase the poweroff delay to
5 seconds to compensate for not being able to issue the ATA SLEEP command.
Hopefully this is enough time. If not, we will have to re-disable PM
entirely when we detect these popular adapters. Thankfully that is now
just an #ifdef away.
Change-Id: I4112b9acb965973d81f70483bd9d595461c7301c
It's possible to get up to 3000mAh batteries for this device, although
it requires that you use an iFlash adapter to make enough space.
Signed-off-by: Caleb Connolly <caleb@connolly.tech>
Change-Id: I0d0d02aa30caffcae4a7e8c805516a1266eef359
The FC1307A ATA->SD chipset (used by the common iFlash adapters)
doesn't support mandatory ATA power management commands, leading to
massive data corruption if they were issued.
A workaround was identified (54629073ae) that basically disabled all of
rockbox's power management code for these adapters, which extends well
beyond the specific ATA commands issued.
This patch moves the gating test to the issuance of the actual SLEEP,
so that the rest of rockbox's PM code can function as intended. This
allows the device to get powered down when idle, yielding potentially
significant improvements in battery life.
Change-Id: Ia13e2405243fe5efe6f68c3a549ab4933567790b
* PREV/NEXT now swapped so they do what is expected in most contexts
* List and setting context retains prior behavior
* Enable the ADC that reads the headset remote and map the keys.
* As ADC-based remote "events" arrive as press/release pairs,
delay the button release.
Change-Id: I22d4eac3bfe1573b50eca795cf377bdafdeb5336
affects all hiby targets, fiiom3k, and ibasso dx50/dx90
As well as deduplicating a small pile of code, this also implements
hysteresis so we're not doing a sysfs read/lookup multiple times
back-to-back every time the power management tick fires.
Change-Id: I2f7672acbb36341becf67e07960c24c681270d09
This means we will no longer send them routinely and instead rely on
the HID driver to send them when the host requests it. This also
moves the reporting out of the power management code where it probably
did not belong in the first place.
Change-Id: I9c8420e81897f1f6caaa55ffacc7525589f1ef75
Previously these were placed in DRAM, which is overwritten by RoLo
when it loads a new image, but RoLo must call commit_discard_idcache()
after loading the image.
Change-Id: I5dcc4ca711b774166f83c668695edbcabfab2604
This allows rockbox to report its battery status through the
HID Battery Strength method that is available through the
Device Controls usage page.
Change-Id: Ia7a7dd9b9d476dd9df5a5f5becabc5ae823e9a89
SSDs that respect powermgmt commands should be treated the same, as the
powermgmt commands are an important part of ensuring it's safe to shut
down.
And greatly expand the comment explaining things.
Change-Id: Ia52b99fca802f495422b5ee097390a72dbc28f61
Commit 5462907 made sure that SLEEP commands weren't issued on devices that don't support ATA power management commands (e.g. certain CF->SD converters including several iFlash models).
Since Rockbox waits for the disk to become inactive in shutdown_hw(), which won't happen in this case, the OS would previously stall during the shutdown process until a timeout was reached.
Change-Id: I03bb05f6f6401bb8f0da5d0b76bd3f07681fdc06
The filesystem API often passes in unaligned receive buffers, and some
code (eg BMP reader) processes data in-place, leading to data loss when
we dropped the cache.
(And document exactly what we're doing, so we don't go through this again
at $future_date)
Change-Id: If47a7f2148a5a1a43777f0bd3be1bdfe8239e91e
Since that encompasses _all_ of our native targets in a post-archos world,
either replace it with #if (CONFIG_PLATFORM & PLATFORM_NATIVE) or
delete it altogher as appropriate.
Change-Id: I9128a456e850d5c96a9e05806aad3acd923f90c5
In fixing the original bug I tried to optimize discard_dcache_range()
to minimize writeback and inadvertently introduced a second bug, which
typically ends in a TLB refill panic.
It occurs only if the range fits within one cache line, and when both
the start and end of the range are not aligned to a cache line. This
causes ptr to be incremented and end to be decremented, so ptr > end,
and the loop can't terminate.
Change-Id: Ibaac072f1369268d3327d534ad08ef9dcee3db65
- The range-based cache operations on MIPS were broken and only worked
properly when BOTH the address and size were multiples of the cache
line size. If this was not the case, the last cache line of the range
would not be touched!
Fix is to align start/end pointers to cache lines before iterating.
- To my knowledge all MIPS processors have a cache, so I enabled
HAVE_CPU_CACHE_ALIGN by default. This also allows mmu-mips.c to use
the CACHEALIGN_UP/DOWN macros.
- Make jz4760/system-target.h define its cache line size properly.
Change-Id: I1fcd04a59791daa233b9699f04d5ac1cc6bacee7
ATA DMA was enabled for all PP502x targets in d118f47 after previously reported instabilities were thought to have been fixed. The iPod 4G target remains unstable when UDMA 2 is enabled. File system corruption will eventually occur even using stock hardware in normal usage, according to both my own experience and that of several other forum users. UDMA 1 appears to be stable.
Change-Id: I8526bad9e879f5dad5174cfe07cd8828d8b72406
Without this, if a device is left plugged in and idle, unplugging it will
trigger an immediate shutdown.
Change-Id: I65caaa0c1473562ec5d0bb776b01d4d222d69965
Basically no longer treat SCROLL_FWD/BACK as "button" events, instead
relying on the scrollwheel hooks to handle things properly.
Change-Id: I9bf18595ab3ca68e912f6dfb1f2eac2544578e73
