This was spotted while playing with qemu-jz:
1) rockbox reads TECR and TESR which are described as write-only
registers. Datasheet doesn't mention what happens if they are
readed. Apparently this doesn't have fatal side effects.
It comes down to two defines from jz4740.h
__tcu_stop_counter(n) and __tcu_start_counter(n) which use
read-modify-write sequence.
2) rockbox accesses out of bound offset 0xd4 in DMA memspace.
It comes from dis_irq() in system-jz4740.c. NUM_DMA is 6 but
DMA channels are 0-5 so (irq <= IRQ_DMA_0 + NUM_DMA)) bound
check is wrong.
This are *NOT* tested on device.
Change-Id: I29dff6a4f828030877b7d50fbcc98866478b9e3d
Reviewed-on: http://gerrit.rockbox.org/338
Reviewed-by: Bertrik Sikken <bertrik@sikken.nl>
Tested-by: Purling Nayuki <cyq.yzfl@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
This patch adds to YP-R0 (and other future targets using Linux
framebuffer) the ability to use LCD_ENABLE to save some CPU cycles
while display is powered off.
This patch also changes the way to toggle LCD power: now using
a proper ioctl call, slightly more efficient.
Change-Id: I544de77f5abd4ac1c13d3fe3a6e40a30f7c0bece
Reviewed-on: http://gerrit.rockbox.org/410
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
The GPIO device file wasn't closed due to this. This wasn't a big deal
because the device powers off shorty afterwards anyway.
Change-Id: I9a6b4d57d32627157323b4883e47b8812f5dcb4d
As per title this patch aims at splitting common target
code and specific target code in a better way to
support future ports within the same environment
(e.g. Samsung YP-R1 where the Linux and the SoC
are the same, with differences in hardware devices
handling)
Change-Id: I67b4918c46403b184d3d8f42ab5aae7d01037fd0
Reviewed-on: http://gerrit.rockbox.org/409
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
commit_discard_dcache_range() is used in sd, lcd and pcm drivers
to handle transfers form/to data buffers so this should not introduce
any problems. It is reported to fix pop noise observed on some hifimans.
We apparently don't fully understand cache handling on this platform.
Change-Id: I436d291509f91d16a13d10965a28171fb27574ab
In commit_discard_idcache(), cache lines were marked as invalid. When
some cache lines are marked as invalid, memory corruption can occur.
This caused instability when using PP502x ATA DMA because of the many
more calls to that function. Here, commit_discard_idcache() is changed
to avoid the problem. Also, the cache is filled after being enabled to
to ensure there are never any cache lines that aren't marked as valid.
Change-Id: Ia26300acef6b0573c1f40299c496ee5cbda3dac8
Reviewed-on: http://gerrit.rockbox.org/339
Reviewed-by: Szymon Dziok <b0hoon@o2.pl>
Tested-by: Szymon Dziok <b0hoon@o2.pl>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
The SD driver doesn't initialised drives at the beginning but
upon request to handle removable drives. Since means that the
init should call init_drive() and not init_sd_card() otherwise
the check for WINDOW flag is bypasses. This breaks the zenxfi3
bootloader and has been overlooked for some time.
Change-Id: I7325f7164d16d7e7e54eeb4645e98517a08e0836
Move to a table based approach (scales better) and distinguish
between upward changes (increase frequency) and downward changes
(decrease frequency). This provides a better ordering of
operations and in particular it allows to avoid changing the
regulator while running at low speed since it takes a long time !
This should result in a much smoother scaling.
Change-Id: Iad7e5b61277e215f31c07877fbbad07ddde1171f
For some reason it is the responsability of the driver to send
this event so do it. This might fix some non-updating screens.
Change-Id: Ib5fdc94bf266c3497a8ac4e89d0418c0e876ff9f
The lcd kind is always set to st7783 in case we can't read the ID
so don't bother handling impossible cases
Change-Id: I352fd43b26068b460e69190d37c4cd4627e1db9a
The flip and invert settings can potentially be reset to their
value accross a disable/enable cycle, so save the value of the
impacted registers and apply it after each enable. Also avoid
poking registers when the lcd is not on.
Change-Id: Ica98f166c060aade7eb205f5628b58aae692024f
When chaging the cpu and memory frequency we need to disable the
external memory interface (EMI) for a small time. This can
underflow the dma and cause some breakage. Hopefully the SSP
controller handles this gracefully by stopping the clock and the
I2C probably handles this naturally because the clock can be
streched anyway. However the LCDIF has a special setting for this
which needs to be enable, otherwise it will send garbage to the
LCD. No other block is known to suffer from this currently but
this issue might have more unexpected consequences.
Change-Id: Ide154cad87929f2bf6cc419ac1d2ff33e30eec66
The manual recommands to tweak the arm cache settings on frequency
changes. The meaning of these values is undocumented but 0 seems
to be a safe value for all frequencies whereas 3 seems to be valid
only for low frequencies (<=64MHz ?)
Change-Id: Iaa8db4af8191010789cf986b1139ff259d73e2ed
CPU frequency scaling is basically useless without scaling the
memory frequency. On the i.MX233, the EMI (external memory
interface) and DRAM blocks are responsable for the DDR settings.
This commits implements emi frequency scaling. Only some settings
are implemented and the timings values only apply to mDDR
(extracted from Sigmatel linux port) and have been checked to
work on the Fuze+ and Zen X-Fi2/3. This feature is still disabled
by default but I expected some battery life savings by boosting
higher to 454MHz and unboosting lower to 64MHz.
Note that changing the emi frequency is particularly tricky and
to avoid writing it entirely in assembly we rely on the compiler
to not use the stack except in the prolog and epilog (because
it's in dram which is disabled when doing the change) and to put
constant pools in iram which should always be true if the
compiler isn't completely dumb and since the code itself is put
in iram. If this proves to be insufficient, one can always switch
the stack to the irq stack since interrupts are disabled during
the change.
Change-Id: If6ef5357f7ff091130ca1063e48536c6028f23ba
pcm_dma_apply_settings(): sets the configured PCM frequency,
all native CS42L55 sample rates are available.
Change-Id: I2fcd5581457a669c3044516804cb64fb972218d0
Actually Rockbox does not use this mode, it is supported by
other iPods, so implemented on Classic as well.
Change-Id: Ia6578506df27a95a7f7522b3034b764631a8bb3a
Scale battery voltage ADC readings by 1023 instead of 1000,
using ADC1 (substractor) instead of ADC0 (multiplicator) to
get better resolution.
Percent charge/discharge tables are also modified to return
a similar value than the old ones.
Change-Id: I2951c75faa02f4302599ec24f9156cfd209c36eb
On heavy storage operations (like database update), the ssp dma
irq can be fired around ~10000/sec.
Change-Id: I0e33df6258e051abd4fe110a0f408a19671cd8ad
Do low level power init in system_init(). This can be needed
since imx233 must be able to frequecy scale atfer system_init()
and kernel_init() and this is only possible if power system was
initialised.
Change-Id: I27c66ec0dccd60bda26a45be24683c0bfe72c6da
The current code uses the msec irq to collect statistics and
detect irq storms (debug). But this irq is triggered 1000 times
per sec and we don't need that accuracy. This commit removes the
msec irq and use the tick timer instead which is triggered only
100 times per second.
Change-Id: If14b9503c89a3af370ef322678f10e35fafb4b8a
The lcd driver does not wait for the refresh to be done to return
from lcd_update(). This means that changing a register is unsafe
if done in the middle of the redraw. This could happen when
disabling the lcd for example. Make sure it doesn't happen by
waiting for the lcdif to be ready.
Change-Id: I43ec62a637dd61c3b2a3a6e131c1a9e8035524b1
When changing the cpu frequency, it is important to make sure that
HBUS stays at a reasonable frequency otherwise the chip will
crash. Special care is needed about auto-slow and clk_p/clk_h
ratio on intermediate steps.
Change-Id: Ief9f68ddf286caabe75c879718dac5027ab1560f
Make sure DCDC is running at boot (it is disabled by default when
5V is present and we don't want to rely on the bootloader to
change this).
When changing the voltage on a regulator, it usually takes 2ms for
the voltage to stabilize. In DCDC mode, there is an irq to notify
about the event so use it ! This is especially important when
changing cpu frequency because increasing the cpu freq while the
voltage is rising is unreliable.
Change-Id: Icfe9ef3ee90156d1e17da0820d9041859f7f3bca
HBUS uses the same field for integer and fractional dividers, the
choice is made by a bit. Make sure both are changed together,
otherwise this could result in the wrong divider to be used and in
HBUS freq to be too low or too high (very bad).
Change-Id: I253d8eeee26c5038868b729c4f791511295a39f0
Ideally someone will go through and make a graphic for the 6G, but as it looks nearly identical to the Video its not a huge deal.
Change-Id: If507c6d4f01eb0b1e5fc2f15f6a0e5a3195006c6
Uninitialized struct scroll which is used to pass state between
scrollstrip ISR and button_read_device() can bomb out whole
button subsytem.
Change-Id: I3b415c22cfee4181b2132cddaeff68797c7cc0ea
If interrupts trigger during cache invalidation this could cause memory
corruption. This should be right fix for commit_discard_idcache in
contrast to 72ebcbf and c1ec1ec.
Change-Id: I141fb585004d4a1967b0a03bc37db3964d886564
Reviewed-on: http://gerrit.rockbox.org/345
Tested-by: Andrew Ryabinin <ryabinin.a.a@gmail.com>
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
It seems something wrong with cache handling in rk27xx. OF always disable cache
before invalidating cache ways, therefore, now we do the same.
Hopefully this will fix cache handling, but I couldn't contend that it's really so.
Change-Id: I967c18211f0ddff689b6a17579fbe8685277f132
This is work from FS#12431 synced to current HEAD and slightly
tweaked (gcc 4.6.2 -> 4.6.3, binutils 2.21.1 -> 2.22)
Change-Id: I76af91e80ac2a9c16a776c7f0a33cc51603bbf9b
The running count is only 16-bit wide, since the always tick
setting derives from the crystal clock at 24MHz the user timer
cannot be set lower than ~300Hz which is already too high.
Switch to the 32KHz crystal source to fix this.
Change-Id: Ie7775460b17ea7ab331738734e3d688ad5563857
Several HM-801 DAPs have another buttons circuit.
This patch adds support for such devices so they could work properly.
Change-Id: Ic49e8e46b3e785b91c7c4706003fac3dbc20ae59
Uses register polling method to decide when it's time to decode
RDS packets.
Change-Id: I1d3cc995ea3350ec7b101438b8f2027130d4a4c9
Reviewed-on: http://gerrit.rockbox.org/320
Reviewed-by: Lorenzo Miori <memorys60@gmail.com>
Tested-by: Lorenzo Miori <memorys60@gmail.com>
Reviewed-by: Thomas Martitz <kugel@rockbox.org>
Tested-by: Thomas Martitz <kugel@rockbox.org>
We should cast to (volatile uint32_t*) here, because attempt to refer to volatile
object through use of an lvalue with non-volatile-qualified type will result in
undefined behavior.
Change-Id: I1b2e9688af11d3dcba518a5e31865d703b54b635
Use DMA engine for fullscreen updates and bypass mode for partial
updates. This gives major boost on rk27generic:
default ARM:AHB:APB 200💯50
HEAD 1/1: 26.3fps 1/4: 105.0fps
patched 1/1: 116.5fps 1/4: 249.5fps
with freq scalling NORMAL mode ARM:AHB:APB 50:50:50
HEAD 1/1: 13.1fps 1/4: 52.5fps
patched 1/1: 54.5fps 1/4: 119.0fps
Tested on rk27generic noname DAP and on Hifimans.
Change-Id: Id9dd4d2d61542c7ea6b5c6336b170d6357cefde9
This version resembles how OF handle cache invalidates.
This seems to fix mysterious data aborts on plugin/codec loading
after introducing frequency scaling.
Credit goes to mortalis for pinpointing the reason of aborts.
Change-Id: I3477b3f65d593d7b43c36a0b06d863f71f000812
The functions document my reverse engineer findings about nand
controller. This code is commented out and is purely for reference
as FTL scheme is still unknown.
Change-Id: I70edeb4bfb0cbd51b6adc15afa7193dd8f71e8da
Frequency scaling seems to be unstable and causes the device to
freeze. It is unclear why at the moment, perhaps we need to ramp
up the vddd voltage to avoid a false brownout ?
Change-Id: I7aaea9d7c213922a65250fe50775fb785d430226
This does not scale the EMI frequency and keep the processor
betweel 261MHz and 454MHz. It can still be improve. The auto-slow
divisor could still be change, 8 seems reasonable for now
Change-Id: I639bb3f6b7f8efedc7dc58d08127849156eeb1b6
Implemented scheme:
ARM AHB APB
Normal 50 50 50 MHz
Max 200 100 50 MHz
Frequency scaling is disabled on rk27generic due to too
slow lcd updates when running with 50MHz AHB.
battery_bench shows ~1h runtime improvement on hifiman.
Change-Id: I2c6f8acf6d4570c4e14f5bcc72280b51ce13c408
Remove the old debug stuff about VDDx and add a clean api to
get/set the regulator (VDDD, VDDA, VDDIO, VDDMEM). This is useful
for proper frequency scaling.
Change-Id: Ia5a1a712fd66652a8ad9601ed00db31aba5a7561
Implement cache aligned transfer of more than one sectors. The
current code now transfers almost all data at once by moving
it within the buffer to make it cache aligned. This greatly
improves the performance of the transfers, especially in mass
storage mode.
Change-Id: Ic6e78773302f368426209f6fd6099089ea34cb16
Further merge drivers by using the same command and data functions.
No use one mutex per drive instead of a global sd lock. Fix the
RCA handling which was different between SD and MMC (shifted 16)
and thus confusing. Add MMC commands definition to the mmc.h
header similarly to the SD one. Change MMC handling a bit by
selecting/deselecting on each transfer like SD, which allows
for several MMC devices in theory and is more uniform.
Change-Id: I7024cb19c079553806138ead75b00640f1d2d95c
Merge sd and mmc drivers into a single sdmmc driver. This allows
some factoring of the code and simplify bug fixing. Also fix the
dma/cache related issue by doing all transfers via a correctly
aligned buffer. The current code is not smart enough to take
advantage of large user buffers currently but at least it is safe!
Change-Id: Ib0fd16dc7d52ef7bfe99fd586e03ecf08691edcd
There are tricky DMA/cache related issue on the imx233 which could
pop up with the old driver. The new one ensures that all dma
tranfers are cache safe by using an intermediate buffer.
Change-Id: I72060682d1c285c83ae16455cfdb62f372b5d687
Reduce DMA maximum transfer size since transfering 64Kb requires
to set a size of 0 and it's not worth adding checks everywhere
to handle this special case. Also add statistics about unaligned
transfer (wrt to cache). Update debug screen accordingly and
simplify it so it can fit smaller screens too.
Change-Id: I18391702f5e100a21f6f8d1ebab28d9f2bd8c66f
operation.
The interal ROM clock seems to be needed to reboot the player, so disabling
it is too dangerous. Hopefully this will prevent problems where crashes during
the abort handler resulted in a stock player that needed the battery to drain
in order to reboot.
Change-Id: I7d1e64743dde15b64d718ad3255dada3d570736f
The main reason for this is to be able to downscale the sdl app, which
when used for designing themes for android tends not to fit on laptop
screens these days.
Change-Id: Ib52731dbebcdd03a572be7754c157471165eb2df
Basically it uses the default SI4700 radio chip driver, the only thing that's different is the I2C access,
written specifically to interact with my kernel module.
Next things to add are:
- RDS support!
Change-Id: I0ed125641e00f93124d7a34f90dd508e7f1db5a4
Signed-off-by: Lorenzo Miori <memorys60@gmail.com>
Refactor native/hosted implementation seperation while at it
(no wrappers starting with _ anymore).
Change-Id: If68ae89700443bb3be483c1cace3d6739409560a
Apparently I got the "just-in-case" RXFIFO purge in there before the
RXFIFO was enabled, causing severe hardware spasms.
Change-Id: I2ea4b6d28e06372b61cb3f21ab2fce71dd408213
Implement PLL enabling/disable and unconditionally power the PLL
on startup. This is needed at least on the Zen X-Fi2.
Change-Id: Ib9ddfdeaf973cedded4b3586dd16aa95a61e78ba
1) Change the image with a clean one
2) add keymaps indication
Change-Id: I0d3fff317406809523fb34282df058fe2e074a2c
Reviewed-on: http://gerrit.rockbox.org/173
Reviewed-by: Peter D'Hoye <peter.dhoye@gmail.com>
Tested-by: Peter D'Hoye <peter.dhoye@gmail.com>
Because DMA descriptors needs to be committed and discarded from
the cache, if they are not cache aligned and/or if their size
is not a multiple of cache ligne, nasty side effects could occur
with adjacents data. The same applies to DMA buffers which are
still potentially broken. Add a macro to ensure that these
constraints will not break by error in the future.
Change-Id: I1dd69a5a9c29796c156d953eaa57c0d281e79846
Sometimes I do want to update outside the screen boundaries and it was
messing it up; such things should not cause display problems.
Change-Id: Ic9deec609b19e5a1c603601b20c66599dd44f892
The freescale firmware partitions has a lots of quirks that
need to be dealt with, so do it the proper way.
Change-Id: I8a5bd3fb462a4df143bc6c931057f3ffedd4b3d3
The icoll code now has an IRQ storm detection mechanism which
will prevent the device from hard freezing in case it happen.
Change-Id: I9861238dce61d29af1e48f9c534ec63a7f23465c
I successfully identified the STC/RDS pin as B2P27.
Strangely the OF uses polling instead of interrupts
but since they routed it, let's use it! On the fuze+
the fmradio i2c uses bit toggling so we can't read
the RDS data in the interrupt context. Instead we
defer the work to a thread.
Change-Id: Iedfa425320e6c91b4351b72e97c732696bdb2b73
Reviewed-on: http://gerrit.rockbox.org/236
Reviewed-by: Bertrik Sikken <bertrik@sikken.nl>
Reviewed-by: Amaury Pouly <amaury.pouly@gmail.com>
Past development has proved that one can mistakely use
the same pin for two uses without noticing. Since this
causes extremely hard to find bugs, the infrastructure
will allow to register pin uses and panic when a conflict
is detected. The pinctrl debug now shows the pin uses
when its support is compiled in.
Change-Id: Idb2d5235ce09207d77aa474d6f158e72b933761a
It was only needed by the old arm toolchain that we no longer use or support.
Change-Id: Id0e6c67477f8834a637079b03cde5fbf9da68b1c
Reviewed-on: http://gerrit.rockbox.org/233
Reviewed-by: Nils Wallménius <nils@rockbox.org>
Player-specific code remaining: usb_drv_(init,exit)
The iPods lack a MMU, so:
- physical, virtual, and uncached addresses are identical
- since we can't access uncached memory we discard caches when receiving data
Still not quite reliable on nano2g
Change-Id: Iebb79df64818b9ae3b68eccb8be8975ebd6c21ea
- Add BUTTON_POWER.
- hm60x: Rename BUTTON_PLAY to more proper BUTTON_SELECT, which will make it
possible to unify hm60x and hm801 keymaps in some plugins.
Change-Id: I84715cdbc79d00c1bc2e8e6bd492159ad3c3422b
Remove the implementations of all exceptions handlers from the
various crt0.S files and have a single implementation in system-arm.h
The new implementation is weak so that it can be overwritten by some
specific code (like the unwinder)
Change-Id: Ib3e041ed6037376bbe0e79286057e1051640dd90
Reviewed-on: http://gerrit.rockbox.org/205
Reviewed-by: Marcin Bukat <marcin.bukat@gmail.com>
The scrolling code cannot differentiate between the BUTTON_TOUCHSCREEN post
from normal touches and the one posted in the timeout callback.
To fix introduce a global special button (BUTTON_REDRAW) that results
in the desired redraw. This existed already as a local kludge for android
and is now generalized.
Change-Id: I6bfa6c66431c48f5042fcd8fce2ea72cd3457f58
The warnings 1207c7b was supposed to get rid of are sim-only. This
means the binsize argument used for the _FORTIFY_SOURCE fix did not
apply at all. This one actually checks the return values.
Change-Id: Ic4cd8c25de4305310baa868c077a66981cdfcb4b
This patch implements HAVE_ADJUSTABLE_CPU_FREQ, it modifies the
following parameters when CPU is unboosted:
- s5l8702 voltage is decreased: 1.200V -> 1.050V
- CPU frequency is divided by 4: 216MHz -> 54MHz
- AHB frequency is divided by 2: 108MHz -> 54MHz
Change-Id: I2285b83efb7e1567864ac288f2d4ba55f058f7c5
Configures GPIO ports to detect holdswitch status instead of
polling the PMU via I2C, this fixes some random crashes
Change-Id: I407c9ca4c2c9203842f9e774b1c8d0455d59048c
Reviewed-on: http://gerrit.rockbox.org/194
Reviewed-by: Michael Giacomelli <giac2000@hotmail.com>
libs in $ROOT/lib now add to $(CORE_LIBS) and $(EXTRA_LIBS) and are
automatically linked by the core and codecs/plugins respectively.
Change-Id: Iff482c792a8c8142718f6a16a450c6e2f1497c9a
For now it contains explicit SDRAM setup, cutting clock for unused
modules and turning off unused PLLs. This improves slightly mem
throughput as well as saves quite a bit of power.
Change-Id: I19a2827ac90a6868856c676fbe1e051c42f0d608
* rename some java methods (to update(), initialize())
* re-create the ByteBuffer object from the framebuffer on every update.
This is needed now since 2c71aa9 added the possiblity for lcd_framebuffer to change.
* do so, along with the creation of the dirty Rect object, in native code.
Change-Id: Id39ea8e4b6148987c5f216a87e0ff3c8e7babe92
Especially when unzipping rockbox.zip, the native code can be initialized
a lot later than the java code. The java code needs to be prevented from
accessing rockbox structures (e.g. current_tick, event queues) before they're
ready.
This commit adds wait_rockbox_ready() and fixes dodgy behavior of starting
rockbox via widget play button, headset remote buttons or multimedia keys.
Also fixes wrong small list items before first redraw.
Change-Id: I1caf925e829a9c1c6bb6e0016d5c80574574c91e
