Michael Sevakis
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90aafeae67
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Fix yellow. Left an unused temp variable.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29117 a1c6a512-1295-4272-9138-f99709370657
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2011-01-22 21:11:29 +00:00 |
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Michael Sevakis
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0a98e8af9d
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i.MX31: Allow interrupts in thread context, not just ISR context, during the lengthy DVFS voltage ramp-up delay. Also, explicitly enable them just before mc13783_init since that does anyway because of the PMIC write inside it.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29116 a1c6a512-1295-4272-9138-f99709370657
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2011-01-22 21:04:25 +00:00 |
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Michael Sevakis
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98246b82b9
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i.MX31: Add a debug menu to play around with DVFS/DPTC settings for fun, testing or benchmarking purposes. Can set the CPU frequency working point, whether DPTC voltage scaling is enabled and change the software-programmable load tracking weights.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29113 a1c6a512-1295-4272-9138-f99709370657
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2011-01-22 16:58:17 +00:00 |
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Michael Sevakis
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9d97ee1b54
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Gigabeat S/i.MX31: Take care of an interrupt priority inversion that can happen during PCM callback lockout when DVFS switches frequecies during the lockout, preventing a thread from unlocking the callback until DVFS finishes, causing an SSI FIFO underrun. Hadn't thought of an acceptable way to deal with it before.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28996 a1c6a512-1295-4272-9138-f99709370657
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2011-01-07 20:40:36 +00:00 |
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Michael Sevakis
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e286b0bbc0
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Remove atomic register bit manipulation functions from i.MX and s3c target code and introduce generic functions for ARM (bitmod32, bitset32, and bitclr32). Multiprocessor support is possible but just not implemented at the moment, only interrupt lockout.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@27188 a1c6a512-1295-4272-9138-f99709370657
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2010-06-30 02:02:46 +00:00 |
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Michael Sevakis
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60f843bf18
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Configure Gigabeat S with EABI compiler by default. Implement the INIT section that this enables (due to selective need for long calls). Remove pcm_postinit from INIT section since it's asynchronous. Disable strict aliasing on SPC codec for now just to shut it up.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26779 a1c6a512-1295-4272-9138-f99709370657
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2010-06-11 14:39:35 +00:00 |
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Michael Sevakis
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0defb8483c
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Gigabeat S bootloader: Fix archaic call placement in dptc_stop which hangs the bootloader before jumping to FW. Let the backlight LED ramp up after unplugging USB which just looks better.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25840 a1c6a512-1295-4272-9138-f99709370657
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2010-05-06 04:45:05 +00:00 |
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Michael Sevakis
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a36a498c57
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i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657
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2010-05-06 03:23:51 +00:00 |
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Michael Sevakis
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630b4fc555
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i.MX31/Gigabeat S: The nested IRQ code was just totally wrong and not actually working anyway (which is why it wasn't crashing). AVIC doesn't seem truthful about priority of current ISR either :\. Sometimes there were channel swaps during really active DVFS due to FIFO underflow from a needed long delay in the ISR (100us, and IIS TX only has 45us reserve) and DMARQ *must* be serviced low-latency. Get it doing as was intended.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25822 a1c6a512-1295-4272-9138-f99709370657
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2010-05-05 07:15:20 +00:00 |
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Michael Sevakis
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4048a1cf4b
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Merely correct a comment.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25802 a1c6a512-1295-4272-9138-f99709370657
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2010-05-04 10:43:32 +00:00 |
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Michael Sevakis
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5edcb11f44
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i.MX31/Gigabeat S: Just a little paranoid change to switcher write to active regulators method, to keep things localized a bit more from global data pool, for safety's sake. It's going to Mars afterall.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25801 a1c6a512-1295-4272-9138-f99709370657
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2010-05-04 10:37:06 +00:00 |
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Michael Sevakis
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931e06de64
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i.MX31/Gigabeat S: Actually enable DPTC which can set optimal voltage for 528MHz. Requires an SPI and PMIC interface rework because of the low-latency needs for the DPTC to work best with minimal panicing. SPI can work with multitasking and asynchronously from interrupt handlers or normal code.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25800 a1c6a512-1295-4272-9138-f99709370657
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2010-05-04 10:07:53 +00:00 |
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Michael Sevakis
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11cca264ff
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i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
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2010-04-23 15:32:50 +00:00 |
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Michael Sevakis
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87eea33def
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Gigabeat S (imx31): Begin voltage and frequency scaling code. For now, to avoid overdrive voltage, just lower core voltage to 1.35V since voltage scaling shouldn't be required for frequencies lower than 399 MHz (according to Freescale BSP, which set all working points to 1.35V for those frequencies). Perhaps battery life will improve as well (cross fingers :).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25506 a1c6a512-1295-4272-9138-f99709370657
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2010-04-07 03:43:48 +00:00 |
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