i.MX31: Add a debug menu to play around with DVFS/DPTC settings for fun, testing or benchmarking purposes. Can set the CPU frequency working point, whether DPTC voltage scaling is enabled and change the software-programmable load tracking weights.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29113 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis
parent
aed6205831
commit
98246b82b9
6 changed files with 412 additions and 118 deletions
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@ -2345,6 +2345,9 @@ static const struct the_menu_item menuitems[] = {
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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{ "CPU frequency", dbg_cpufreq },
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#endif
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#if CONFIG_CPU == IMX31L
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{ "DVFS/DPTC", __dbg_dvfs_dptc },
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#endif
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#if defined(IRIVER_H100_SERIES) && !defined(SIMULATOR)
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{ "S/PDIF analyzer", dbg_spdif },
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#endif
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@ -29,6 +29,7 @@
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#include "adc.h"
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#include "ccm-imx31.h"
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#include "dvfs_dptc-imx31.h"
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#include <stdio.h>
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bool __dbg_hw_info(void)
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{
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@ -242,4 +243,148 @@ bool dbg_ports(void)
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if (button_get_w_tmo(HZ/10) == (DEBUG_CANCEL|BUTTON_REL))
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return false;
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}
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}
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}
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bool __dbg_dvfs_dptc(void)
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{
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int ltwlevel;
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unsigned long ltdetect;
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int dvfs_wp, dvfs_mask;
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bool dptc_on;
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int i;
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char buf[32];
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unsigned long ltw[4];
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bool ltwassert[4];
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lcd_clear_display();
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lcd_setfont(FONT_SYSFIXED);
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dvfs_mask = dvfs_level_mask();
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dvfs_wp = dvfs_enabled() ? -1 : (int)dvfs_get_level();
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dptc_on = dptc_enabled();
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dvfs_get_gp_sense(<wlevel, <detect);
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while (1)
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{
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int line = 0;
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int button = button_get_w_tmo(HZ/10);
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if (dvfs_wp < 0)
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strcpy(buf, "Auto");
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else
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snprintf(buf, sizeof(buf), "%d", dvfs_wp);
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lcd_puts(0, line, "[DVFS/DPTC]");
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line += 2;
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lcd_putsf(0, line, "CPU freq. point (Up/Dn) : %s", buf);
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line += 2;
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lcd_putsf(0, line, "DPTC volt. scale (Play) : %s",
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dptc_on ? "Enabled" : "Disabled");
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line += 2;
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lcd_putsf(0, line, "GP load level (Vol +/-) : %d", ltwlevel);
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line += 2;
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lcd_puts(0, line, "----------------------------------------");
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line += 2;
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lcd_putsf(0, line++, "Frequency: %dHz", cpu_frequency);
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i = dvfs_dptc_get_voltage();
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lcd_putsf(0, line++, "Voltage : %d.%03d V", i / 1000, i % 1000);
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for (i = 0; i <= 3; i++)
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{
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ltw[i] = dvfs_get_lt_weight(i + DVFS_LT_SIG_DVGP0);
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ltwassert[i] = dvfs_get_gp_bit(i + DVFS_DVGP_0);
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}
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lcd_putsf(0, line++, "GPW (3-0): %lu%lu%lu%lu %c%c%c%c",
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ltw[3], ltw[2], ltw[1], ltw[0],
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ltwassert[3] ? 'y' : 'n',
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ltwassert[2] ? 'y' : 'n',
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ltwassert[1] ? 'y' : 'n',
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ltwassert[0] ? 'y' : 'n');
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line += 2;
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lcd_puts(8, line, "(Press SELECT to revert)");
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switch (button)
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{
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case DEBUG_CANCEL|BUTTON_REL:
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return false;
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/* CPU frequency */
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case BUTTON_UP:
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if (++dvfs_wp >= DVFS_NUM_LEVELS)
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{
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/* Going back to automatic */
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dvfs_wp = -1;
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dvfs_start();
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}
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else
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{
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if (dvfs_wp == 0)
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{
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/* Going to manual setting */
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dvfs_stop();
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}
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/* Skip gaps in mask */
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while (((1 << dvfs_wp) & dvfs_mask) == 0) dvfs_wp++;
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dvfs_set_level(dvfs_wp);
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}
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break;
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case BUTTON_DOWN:
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if (--dvfs_wp == -1)
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{
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/* Going back to automatic */
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dvfs_start();
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}
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else
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{
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if (dvfs_wp <= -2)
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{
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/* Going to manual setting */
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dvfs_stop();
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dvfs_wp = DVFS_NUM_LEVELS - 1;
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}
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/* Skip gaps in mask */
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while (((1 << dvfs_wp) & dvfs_mask) == 0) dvfs_wp--;
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dvfs_set_level(dvfs_wp);
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}
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break;
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/* GP Load tracking */
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case BUTTON_VOL_UP:
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if (ltwlevel < 28)
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dvfs_set_gp_sense(++ltwlevel, ltdetect);
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break;
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case BUTTON_VOL_DOWN:
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if (ltwlevel > 0)
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dvfs_set_gp_sense(--ltwlevel, ltdetect);
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break;
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case BUTTON_PLAY:
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dptc_on = !dptc_enabled();
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dptc_on ? dptc_start() : dptc_stop();
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break;
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case BUTTON_SELECT:
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dvfs_start();
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dptc_start();
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dvfs_set_gp_sense(-1, 0);
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dvfs_wp = dvfs_enabled() ? -1 : (int)dvfs_get_level();
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dptc_on = dptc_enabled();
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dvfs_get_gp_sense(<wlevel, <detect);
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break;
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}
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lcd_update();
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yield();
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}
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}
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@ -24,5 +24,6 @@
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#define DEBUG_CANCEL BUTTON_BACK
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bool __dbg_hw_info(void);
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bool dbg_ports(void);
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bool __dbg_dvfs_dptc(void);
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#endif /* DEBUG_TARGET_H */
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@ -74,8 +74,6 @@ unsigned int dvfs_nr_up = 0;
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unsigned int dvfs_nr_pnc = 0;
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unsigned int dvfs_nr_no = 0;
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static void dvfs_stop(void);
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/* Wait for the UPDTEN flag to be set so that all bits may be written */
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static inline void wait_for_dvfs_update_en(void)
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@ -279,6 +277,9 @@ static void INIT_ATTR dvfs_init(void)
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iomuxc_set_pin_mux(IOMUXC_GPIO1_5,
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IOMUXC_MUX_OUT_FUNCTIONAL | IOMUXC_MUX_IN_FUNCTIONAL);
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#endif
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/* GP load bits disabled */
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bitclr32(&CCM_PMCR1, 0xf);
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/* Initialize DVFS signal weights and detection modes. */
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int i;
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@ -321,66 +322,6 @@ static void INIT_ATTR dvfs_init(void)
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logf("DVFS: Initialized");
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}
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/* Start the DVFS hardware */
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static void dvfs_start(void)
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{
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int oldlevel;
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/* Have to wait at least 3 div3 clocks before enabling after being
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* stopped. */
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udelay(1500);
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oldlevel = disable_irq_save();
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if (!dvfs_running)
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{
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dvfs_running = true;
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/* Unmask DVFS interrupt source and enable DVFS. */
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avic_enable_int(INT_CCM_DVFS, INT_TYPE_IRQ, INT_PRIO_DVFS,
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CCM_DVFS_HANDLER);
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CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_FSVAIM) | CCM_PMCR0_DVFEN;
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}
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restore_irq(oldlevel);
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logf("DVFS: started");
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}
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/* Stop the DVFS hardware and return to default frequency */
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static void dvfs_stop(void)
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{
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int oldlevel = disable_irq_save();
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if (dvfs_running)
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{
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/* Mask DVFS interrupts. */
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CCM_PMCR0 |= CCM_PMCR0_FSVAIM | CCM_PMCR0_LBMI;
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avic_disable_int(INT_CCM_DVFS);
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if (((CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS) !=
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DVFS_LEVEL_DEFAULT)
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{
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/* Set default frequency level */
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wait_for_dvfs_update_en();
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do_dvfs_update(DVFS_LEVEL_DEFAULT, false);
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wait_for_dvfs_update_en();
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}
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/* Disable DVFS. */
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CCM_PMCR0 &= ~CCM_PMCR0_DVFEN;
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dvfs_running = false;
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}
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restore_irq(oldlevel);
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logf("DVFS: stopped");
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}
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/** DPTC **/
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/* Request tracking since boot */
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@ -540,52 +481,6 @@ static void INIT_ATTR dptc_init(void)
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}
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/* Start DPTC module */
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static void dptc_start(void)
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{
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int oldlevel = disable_irq_save();
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if (!dptc_running)
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{
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dptc_running = true;
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/* Enable DPTC and unmask interrupt. */
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avic_enable_int(INT_CCM_CLK, INT_TYPE_IRQ, INT_PRIO_DPTC,
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CCM_CLK_HANDLER);
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update_dptc_counts(dvfs_level, dptc_wp);
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enable_dptc();
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}
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restore_irq(oldlevel);
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logf("DPTC: started");
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}
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/* Stop the DPTC hardware if running and go back to default working point */
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static void dptc_stop(void)
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{
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int oldlevel = disable_irq_save();
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if (dptc_running)
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{
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dptc_running = false;
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/* Disable DPTC and mask interrupt. */
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CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_DPTEN) | CCM_PMCR0_PTVAIM;
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avic_disable_int(INT_CCM_CLK);
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/* Go back to default working point. */
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dptc_new_wp(DPTC_WP_DEFAULT);
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}
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restore_irq(oldlevel);
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logf("DPTC: stopped");
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}
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/** Main module interface **/
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/* Initialize DVFS and DPTC */
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@ -611,6 +506,64 @@ void dvfs_dptc_stop(void)
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dvfs_stop();
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}
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/* Start the DVFS hardware */
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void dvfs_start(void)
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{
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int oldlevel;
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/* Have to wait at least 3 div3 clocks before enabling after being
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* stopped. */
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udelay(1500);
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oldlevel = disable_irq_save();
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if (!dvfs_running)
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{
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dvfs_running = true;
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/* Unmask DVFS interrupt source and enable DVFS. */
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avic_enable_int(INT_CCM_DVFS, INT_TYPE_IRQ, INT_PRIO_DVFS,
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CCM_DVFS_HANDLER);
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CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_FSVAIM) | CCM_PMCR0_DVFEN;
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}
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restore_irq(oldlevel);
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logf("DVFS: started");
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}
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/* Stop the DVFS hardware and return to default frequency */
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void dvfs_stop(void)
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{
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int oldlevel = disable_irq_save();
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if (dvfs_running)
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{
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/* Mask DVFS interrupts. */
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CCM_PMCR0 |= CCM_PMCR0_FSVAIM | CCM_PMCR0_LBMI;
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avic_disable_int(INT_CCM_DVFS);
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if (((CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS) !=
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DVFS_LEVEL_DEFAULT)
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{
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/* Set default frequency level */
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wait_for_dvfs_update_en();
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do_dvfs_update(DVFS_LEVEL_DEFAULT, false);
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wait_for_dvfs_update_en();
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}
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/* Disable DVFS. */
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CCM_PMCR0 &= ~CCM_PMCR0_DVFEN;
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dvfs_running = false;
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}
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restore_irq(oldlevel);
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logf("DVFS: stopped");
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}
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/* Mask the DVFS interrupt without affecting running status */
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void dvfs_int_mask(bool mask)
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@ -648,6 +601,26 @@ void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value)
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}
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/* Return a signal load tracking weight */
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unsigned long dvfs_get_lt_weight(enum DVFS_LT_SIGS index)
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{
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volatile unsigned long *reg_p = &CCM_LTR2;
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unsigned int shift = 3 * index;
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if (index < 9)
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{
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reg_p = &CCM_LTR3;
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shift += 5; /* Bits 7:5, 10:8 ... 31:29 */
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}
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else if (index < 16)
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{
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shift -= 16; /* Bits 13:11, 16:14 ... 31:29 */
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}
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return (*reg_p & (0x7 << shift)) >> shift;
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}
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/* Set a signal load detection mode */
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void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge)
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{
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@ -662,6 +635,21 @@ void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge)
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}
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/* Returns a signal load detection mode */
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bool dvfs_get_lt_detect(enum DVFS_LT_SIGS index)
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{
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unsigned int shift = 32;
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if ((unsigned)index < 13)
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shift = index + 3;
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else if ((unsigned)index < 16)
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shift = index + 29;
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return !!((CCM_LTR0 & (1ul << shift)) >> shift);
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}
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/* Set/clear the general-purpose load tracking bit */
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void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert)
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{
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if ((unsigned)dvgp <= 3)
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@ -672,6 +660,82 @@ void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert)
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}
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/* Return the general-purpose load tracking bit */
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bool dvfs_get_gp_bit(enum DVFS_DVGPS dvgp)
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{
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if ((unsigned)dvgp <= 3)
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return (CCM_PMCR1 & (1ul << dvgp)) != 0;
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return false;
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}
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/* Set GP load tracking by code.
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* level_code:
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* lt 0 =defaults
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* 0 =all off ->
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* 28 =highest load
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* gte 28=highest load
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* detect_mask bits:
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* b[3:0]: 1=LTn edge detect, 0=LTn level detect
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*/
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void dvfs_set_gp_sense(int level_code, unsigned long detect_mask)
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{
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int i;
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for (i = 0; i <= 3; i++)
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{
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int ltsig_num = DVFS_LT_SIG_DVGP0 + i;
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int gpw_num = DVFS_DVGP_0 + i;
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unsigned long weight;
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bool edge;
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bool assert;
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if (level_code < 0)
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{
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/* defaults */
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detect_mask = 0;
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assert = 0;
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weight = lt_signals[ltsig_num].weight;
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edge = lt_signals[ltsig_num].detect != 0;
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}
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else
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{
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weight = MIN(level_code, 7);
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edge = !!(detect_mask & 1);
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assert = weight > 0;
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detect_mask >>= 1;
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level_code -= 7;
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if (level_code < 0)
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level_code = 0;
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}
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dvfs_set_lt_weight(ltsig_num, weight); /* set weight */
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dvfs_set_lt_detect(ltsig_num, edge); /* set detect mode */
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dvfs_set_gp_bit(gpw_num, assert); /* set activity */
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}
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}
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/* Return GP weight settings */
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void dvfs_get_gp_sense(int *level_code, unsigned long *detect_mask)
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{
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int i;
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int code = 0;
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unsigned long mask = 0;
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for (i = DVFS_LT_SIG_DVGP0; i <= DVFS_LT_SIG_DVGP3; i++)
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||||
{
|
||||
code += dvfs_get_lt_weight(i);
|
||||
mask = (mask << 1) | (dvfs_get_lt_detect(i) ? 1 : 0);
|
||||
}
|
||||
|
||||
if (level_code)
|
||||
*level_code = code;
|
||||
|
||||
if (detect_mask)
|
||||
*detect_mask = mask;
|
||||
}
|
||||
|
||||
|
||||
/* Turn the wait-for-interrupt monitoring on or off */
|
||||
void dvfs_wfi_monitor(bool on)
|
||||
{
|
||||
|
|
@ -700,21 +764,83 @@ unsigned int dvfs_get_level(void)
|
|||
}
|
||||
|
||||
|
||||
/* Is DVFS enabled? */
|
||||
bool dvfs_enabled(void)
|
||||
{
|
||||
return dvfs_running;
|
||||
}
|
||||
|
||||
|
||||
/* Get bitmask of levels supported */
|
||||
unsigned int dvfs_level_mask(void)
|
||||
{
|
||||
return DVFS_LEVEL_MASK;
|
||||
}
|
||||
|
||||
|
||||
/* If DVFS is disabled, set the level explicitly */
|
||||
void dvfs_set_level(unsigned int level)
|
||||
{
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
unsigned int currlevel =
|
||||
(CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS;
|
||||
|
||||
if (!dvfs_running && level < DVFS_NUM_LEVELS && level != currlevel)
|
||||
set_current_dvfs_level(level);
|
||||
if (!dvfs_running && level < DVFS_NUM_LEVELS)
|
||||
{
|
||||
unsigned int currlevel =
|
||||
(CCM_PMCR0 & CCM_PMCR0_DVSUP) >> CCM_PMCR0_DVSUP_POS;
|
||||
if (level != currlevel && ((1 << level) & DVFS_LEVEL_MASK))
|
||||
set_current_dvfs_level(level);
|
||||
}
|
||||
|
||||
restore_irq(oldlevel);
|
||||
}
|
||||
|
||||
|
||||
/* Start DPTC module */
|
||||
void dptc_start(void)
|
||||
{
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
if (!dptc_running)
|
||||
{
|
||||
dptc_running = true;
|
||||
|
||||
/* Enable DPTC and unmask interrupt. */
|
||||
avic_enable_int(INT_CCM_CLK, INT_TYPE_IRQ, INT_PRIO_DPTC,
|
||||
CCM_CLK_HANDLER);
|
||||
|
||||
update_dptc_counts(dvfs_level, dptc_wp);
|
||||
enable_dptc();
|
||||
}
|
||||
|
||||
restore_irq(oldlevel);
|
||||
|
||||
logf("DPTC: started");
|
||||
}
|
||||
|
||||
|
||||
/* Stop the DPTC hardware if running and go back to default working point */
|
||||
void dptc_stop(void)
|
||||
{
|
||||
int oldlevel = disable_irq_save();
|
||||
|
||||
if (dptc_running)
|
||||
{
|
||||
dptc_running = false;
|
||||
|
||||
/* Disable DPTC and mask interrupt. */
|
||||
CCM_PMCR0 = (CCM_PMCR0 & ~CCM_PMCR0_DPTEN) | CCM_PMCR0_PTVAIM;
|
||||
avic_disable_int(INT_CCM_CLK);
|
||||
|
||||
/* Go back to default working point. */
|
||||
dptc_new_wp(DPTC_WP_DEFAULT);
|
||||
}
|
||||
|
||||
restore_irq(oldlevel);
|
||||
|
||||
logf("DPTC: stopped");
|
||||
}
|
||||
|
||||
|
||||
/* Get the current DPTC working point */
|
||||
unsigned int dptc_get_wp(void)
|
||||
{
|
||||
|
|
@ -722,6 +848,13 @@ unsigned int dptc_get_wp(void)
|
|||
}
|
||||
|
||||
|
||||
/* Is DPTC enabled? */
|
||||
bool dptc_enabled(void)
|
||||
{
|
||||
return dptc_running;
|
||||
}
|
||||
|
||||
|
||||
/* If DPTC is not running, set the working point explicitly */
|
||||
void dptc_set_wp(unsigned int wp)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -124,16 +124,28 @@ void dvfs_dptc_init(void);
|
|||
void dvfs_dptc_start(void);
|
||||
void dvfs_dptc_stop(void);
|
||||
|
||||
void dvfs_start(void);
|
||||
void dvfs_stop(void);
|
||||
bool dvfs_enabled(void);
|
||||
void dvfs_wfi_monitor(bool on);
|
||||
void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value);
|
||||
unsigned long dvfs_get_lt_weight(enum DVFS_LT_SIGS index);
|
||||
void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge);
|
||||
bool dvfs_get_lt_detect(enum DVFS_LT_SIGS index);
|
||||
void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert);
|
||||
bool dvfs_get_gp_bit(enum DVFS_DVGPS dvgp);
|
||||
void dvfs_int_mask(bool mask);
|
||||
void dvfs_set_gp_sense(int level_code, unsigned long detect_mask);
|
||||
void dvfs_get_gp_sense(int *level_code, unsigned long *detect_mask);
|
||||
unsigned int dvfs_level_mask(void);
|
||||
|
||||
unsigned int dvfs_dptc_get_voltage(void);
|
||||
unsigned int dvfs_get_level(void);
|
||||
void dvfs_set_level(unsigned int level);
|
||||
|
||||
void dptc_start(void);
|
||||
void dptc_stop(void);
|
||||
bool dptc_enabled(void);
|
||||
unsigned int dptc_get_wp(void);
|
||||
void dptc_set_wp(unsigned int wp);
|
||||
|
||||
|
|
|
|||
|
|
@ -241,10 +241,10 @@ static const struct dvfs_lt_signal_descriptor lt_signals[16] =
|
|||
{ 0, 0 }, /* DVFS_LT_SIG_ARM11_P_FIQ_B_RBT_GATE */
|
||||
{ 0, 0 }, /* DVFS_LT_SIG_IPI_GPIO1_INT0 */
|
||||
{ 0, 0 }, /* DVFS_LT_SIG_IPI_INT_IPU_FUNC */
|
||||
{ 7, 0 }, /* DVFS_LT_SIG_DVGP0 */
|
||||
{ 7, 0 }, /* DVFS_LT_SIG_DVGP1 */
|
||||
{ 7, 0 }, /* DVFS_LT_SIG_DVGP2 */
|
||||
{ 7, 0 }, /* DVFS_LT_SIG_DVGP3 */
|
||||
{ 0, 0 }, /* DVFS_LT_SIG_DVGP0 */
|
||||
{ 0, 0 }, /* DVFS_LT_SIG_DVGP1 */
|
||||
{ 0, 0 }, /* DVFS_LT_SIG_DVGP2 */
|
||||
{ 0, 0 }, /* DVFS_LT_SIG_DVGP3 */
|
||||
};
|
||||
|
||||
#endif /* _DVFS_DPTC_TARGET_H_ */
|
||||
|
|
|
|||
Loading…
Reference in a new issue