The list is ordered by priority, put the DMA and SD interrupts at
the top
This seems to fix the random freezes on heavy storage operation like
building database or pictureflow cache
The recently added audio interrupt had a priority higher than SD slot on
as3525v1, give it a lower priority
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26160 a1c6a512-1295-4272-9138-f99709370657
When the rest of the code is confirmed to work properly without CPU
frequency changes, it will be possible to reliabily test set_cpu_frequency()
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25924 a1c6a512-1295-4272-9138-f99709370657
Get a bit more battery life (between 30 minutes and 2 hours)
as3525v2: only enabled in bootloader, we need a new binary release anwyway
as3525v1: enabled in rockbox.sansa as well, so we can continue using the
current bootloaders
Flyspray: FS#11246
Author: myself
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25900 a1c6a512-1295-4272-9138-f99709370657
delays after modifying the registers seems not to be needed
moving RAM operation (cpu_frequency variable) before modifying the
register also seems to help
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25754 a1c6a512-1295-4272-9138-f99709370657
We do not need any delay after modifying it in system_init(), so the
same applies in set_cpu_frequency()
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25753 a1c6a512-1295-4272-9138-f99709370657
PCLK doesn't use PLLA as a source but FCLK, so when changing FCLK with
CGU_PROC register, we must change PCLK as well with CGU_PERI register
Operate with 24MHz PCLK (and unboosted FCLK) for Clipv2/Clip+
Use 60MHz on Fuzev2 to keep the display fast enough (still slower than
Fuzev1 though)
µSD seems to function correctly now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25475 a1c6a512-1295-4272-9138-f99709370657
the arm926-ejs doesn't have synchronous/asynchronous/fastbus modes, so
just change CGU_PROC directly
Note: we could use a lower unboosted frequency now
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25417 a1c6a512-1295-4272-9138-f99709370657
Write the setting before enabling the PLL
Fix booting problem (black screen) with Clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25415 a1c6a512-1295-4272-9138-f99709370657
Instead of modifying CGU_PROC to get 24MHz pclk, just switch to fastbus else Clip+ wouldn't boot
Tested on fuzev1/Clip+
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25413 a1c6a512-1295-4272-9138-f99709370657
We do not need a stack pointer at this step, and we are sure to not use
memory not initialized yet (like bss)
Fixes FS#11114 (tested on Fuze)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25229 a1c6a512-1295-4272-9138-f99709370657
Compilation shows a warning for the first argument of the lcd_bitmap() call in show_logo().
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24911 a1c6a512-1295-4272-9138-f99709370657
Differences remaining:
- list of peripherals reset
- CGU_PROC isn't modified on as3525v2
- CGU_PLLA bits aren't known, but we use a known setting for 240MHz
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24868 a1c6a512-1295-4272-9138-f99709370657
Now making the Fuzev2 bootloader build should be pretty easy
TODO:
- write button driver (FlynDice found all buttons already)
- find button light
- decide if lcd-ssd1303.c must be modified for Clip+ using SSP or forked
- check if backlight code works (I copied Clipv2 code)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24520 a1c6a512-1295-4272-9138-f99709370657
Voltage scaling seems to be causing various problems mostly related to issues with the uSD cards.
The increased runtime benefit only amounts to ~30 minutes as currently implemented so it seems prudent to disable it once again at this time.
We still don't understand why the core voltage being lowered would impact the uSD card but in fact it does. The internal cards do not seem to have problems.
I have simply #ifdef'd the voltage scaling code with HAVE_ADJUSTABLE_CPU_VOLTAGE so if you want to use voltage scaling simply define that and the voltage scaling code should run.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24217 a1c6a512-1295-4272-9138-f99709370657
Reuse some code from Clip (LCD) and a lot of code from AS3525
Add a new CPU type : AS3525v2, identical to AS3525 except it's an ARMv5 (arm926-ejs)
SD code still not working
For an unknown reason LCD doesn't work anymore (to be investigated)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24131 a1c6a512-1295-4272-9138-f99709370657
If a panicf() is called while a button is still pressed, the Sansa would
reboot immediately with no chance to see the message
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23490 a1c6a512-1295-4272-9138-f99709370657
INT_GPIOB is not used
INT_MCI0 and INT_GPIOA are only put in the table if needed
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23481 a1c6a512-1295-4272-9138-f99709370657
Still disabled on all targets:
- Fuze and e200v2 see spurious interrupts with no source defined
- Clip/m200v4 deadlock instantly when starting recording (perhaps due to low memory size)
Having the code in SVN will make working on this feature easier
Also add keymaps for Fuze, and correct Frequency section of recording
options : the 22.05kHz limitation of e200v1 and c200v1 doesn't apply to
Sansa AMS (different I2S hardware, unrelated to as3514)
Flyspray: FS#10371
Authors: Fred Bauer and myself
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23476 a1c6a512-1295-4272-9138-f99709370657
Reimplement voltage scaling on AMS Sansas at 1.10v during unboosted operation to improve runtimes. The voltage is now also boosted during disk access if a µSD is present. This prevents the µSD problems we saw on the last implementation.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23193 a1c6a512-1295-4272-9138-f99709370657
They would previously appear like coming from the (disabled) watchdog
module
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@22251 a1c6a512-1295-4272-9138-f99709370657
The input to the ADC is now set to CVDD inside the while loop. If the input gets changed while waiting for the voltage to be read it will now be reset to CVDD before the next read is attempted.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21584 a1c6a512-1295-4272-9138-f99709370657
Lower CVDD core voltage to 1.10 volts when the frequency is less than 200 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21577 a1c6a512-1295-4272-9138-f99709370657
