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as3525v2: add usb driver stub, enable usb phy&core init

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clip+: add USBOTG_ define and enable usb stack

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26132 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Amaury Pouly 2010-05-18 09:58:52 +00:00
parent ed96c935ec
commit 22cfbee274
7 changed files with 364 additions and 5 deletions
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3
firmware/SOURCES
View file

@ -444,6 +444,9 @@ target/arm/as3525/scrollwheel-as3525.c
#else /* AS3535v2 */
target/arm/as3525/sd-as3525v2.c
#endif
#if CONFIG_CPU == AS3525v2
target/arm/as3525/usb-drv-as3525v2.c
#endif
target/arm/as3525/power-as3525.c
target/arm/as3525/usb-as3525.c
target/arm/as3525/dma-pl081.c

1
firmware/export/as3525.h
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@ -110,6 +110,7 @@
#define CCU_VERS (*(volatile unsigned long *)(CCU_BASE + 0x14))
#define CCU_SPARE1 (*(volatile unsigned long *)(CCU_BASE + 0x18))
#define CCU_SPARE2 (*(volatile unsigned long *)(CCU_BASE + 0x1C))
#define CCU_USB_THINGY (*(volatile unsigned long *)(CCU_BASE + 0x20))
/* DBOP */
#define DBOP_TIMPOL_01 (*(volatile unsigned long *)(DBOP_BASE + 0x00))

6
firmware/export/config.h
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@ -276,6 +276,7 @@ Lyre prototype 1 */
#define USBOTG_ARC 5020 /* PortalPlayer 502x */
#define USBOTG_JZ4740 4740 /* Ingenic Jz4740/Jz4732 */
#define USBOTG_AS3525 3525 /* AMS AS3525 */
#define USBOTG_AS3525v2 3535 /* AMS AS3525v2 */
#define USBOTG_S3C6400X 6400 /* Samsung S3C6400X, also used in the S5L8701 */
/* Multiple cores */
@ -912,10 +913,11 @@ Lyre prototype 1 */
#ifndef SIMULATOR
//#define USB_ENABLE_SERIAL
#define USB_ENABLE_STORAGE
//#define USB_ENABLE_STORAGE
#ifdef USB_HAS_INTERRUPT
#define USB_ENABLE_HID
//#define USB_ENABLE_HID
#define USB_ENABLE_CHARGING_ONLY
#else
#define USB_ENABLE_CHARGING_ONLY
#endif

5
firmware/export/config/sansaclipplus.h
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@ -171,10 +171,11 @@
#ifndef BOOTLOADER
#define USB_HANDLED_BY_OF
//#define USB_HANDLED_BY_OF
#define USE_ROCKBOX_USB
/* USB On-the-go */
#define CONFIG_USBOTG USBOTG_AS3525
#define CONFIG_USBOTG USBOTG_AS3525v2
/* enable these for the experimental usb stack */
#define HAVE_USBSTACK

2
firmware/target/arm/as3525/system-as3525.c
View file

@ -325,7 +325,7 @@ void system_init(void)
CGU_PLLASUP = 0; /* enable PLLA */
while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
#if defined(USE_ROCKBOX_USB) || (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
#if (defined(USE_ROCKBOX_USB) && CONFIG_CPU==AS3525) || (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
CGU_COUNTB = 0xff;
CGU_PLLB = AS3525_PLLB_SETTING;
CGU_PLLBSUP = 0; /* enable PLLB */

261
firmware/target/arm/as3525/usb-drv-as3525v2.c Normal file
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@ -0,0 +1,261 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright © 2010 Amaury Pouly
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#include "usb.h"
#include "usb_drv.h"
#include "as3525v2.h"
#include "clock-target.h"
#include "ascodec.h"
#include "as3514.h"
#include <stdbool.h>
#include "panic.h"
#define LOGF_ENABLE
#include "logf.h"
#include "usb-drv-as3525v2.h"
struct usb_endpoint
{
void *buf;
unsigned int len;
union
{
unsigned int sent;
unsigned int received;
};
bool wait;
bool busy;
};
static struct usb_endpoint endpoints[USB_NUM_ENDPOINTS*2];
void usb_attach(void)
{
usb_enable(true);
}
static void usb_delay(void)
{
int i = 0;
while(i < 0x300)
i++;
}
static void as3525v2_connect(void)
{
logf("usb: init as3525v2");
/* 1) enable usb core clock */
CGU_PERI |= CGU_USB_CLOCK_ENABLE;
usb_delay();
/* 2) enable usb phy clock */
CGU_USB |= 0x20;
usb_delay();
/* 3) clear "stop pclk" */
USB_PCGCCTL &= ~0x1;
usb_delay();
/* 4) clear "power clamp" */
USB_PCGCCTL &= ~0x4;
usb_delay();
/* 5) clear "reset power down module" */
USB_PCGCCTL &= ~0x8;
usb_delay();
/* 6) set "power on program done" */
USB_DCTL |= 0x800;
usb_delay();
/* 7) core soft reset */
USB_GRSTCTL |= USB_GRSTCTL_csftrst;
usb_delay();
/* 8) hclk soft reset */
USB_GRSTCTL |= USB_GRSTCTL_hsftrst;
usb_delay();
/* 9) flush and reset everything */
USB_GRSTCTL |= 0x3f;
usb_delay();
/* 10) force device mode*/
USB_GUSBCFG &= ~0x20000000;
USB_GUSBCFG |= 0x40000000;
usb_delay();
/* 11) Do something that is probably CCU related but undocumented*/
CCU_USB_THINGY &= ~0x1000;
usb_delay();
/* 12) reset usb core parameters (dev addr, speed, ...) */
USB_DCFG = 0;
usb_delay();
}
static void core_reset(void)
{
unsigned int i = 0;
/* Wait for AHB master IDLE state. */
while((USB_GRSTCTL & USB_GRSTCTL_ahbidle) == 0);
{
/*udelay(10);*/
sleep(1);
}
/* Core Soft Reset */
USB_GRSTCTL |= USB_GRSTCTL_csftrst;
/* Waits for the hardware to clear reset bit */
while(USB_GRSTCTL & USB_GRSTCTL_csftrst && i < 0x300)
i++;
if(USB_GRSTCTL & USB_GRSTCTL_csftrst)
logf("oops, usb core soft reset hang :(");
/* Wait for 3 PHY Clocks */
/*mdelay(100);*/
sleep(1);
logf("%ld endpoints", USB_GHWCFG2_NUM_EP);
for(i = 0; i < USB_GHWCFG2_NUM_EP; i++)
logf(" EP%d: IN=%ld OUT=%ld", i, USB_GHWCFG1_IN_EP(i), USB_GHWCFG1_OUT_EP(i));
logf("hwcfg1: %08lx", USB_GHWCFG1);
logf("hwcfg2: %08lx", USB_GHWCFG2);
logf("hwcfg3: %08lx", USB_GHWCFG3);
logf("hwcfg4: %08lx", USB_GHWCFG4);
logf("%ld in ep", USB_GHWCFG4_NUM_IN_EP);
logf("tot fifo sz: %ld", USB_GHWCFG3_DFIFO_LEN);
logf("rx fifo sz: %ld", USB_GRXFSIZ);
logf("tx fifo sz: %ld", USB_GNPTXFSIZ >> 16); /* there is no perio ep so print only non-perio */
}
static void core_init(void)
{
/* Reset the Controller */
core_reset();
/* Setup phy for high speed */
/* 1) select utmi */
/* fixme: the clip+ hardware support utmi only, this is useless */
//USB_GUSBCFG &= ~USB_GUSBCFG_ulpi_utmi_sel;
/* 2) select utmi 16-bit wide bus */
USB_GUSBCFG |= USB_GUSBCFG_phy_if;
/* 3) core reset */
/* fixme: linux patch says the phy parameters survive the soft reset so
* perhaps this part can be done only one type but I don't know
* what happened when phy goes to standby mode and clock are disabled */
core_reset();
/* fixme: at this point, the linux patch sets ulpi bits to 0 on utmi selection
* but the clip+ hardware does not support it so don't bother with
* that */
/* fixme: the current code is for internal DMA only, the clip+ architecture
* define the internal DMA model */
/* Set burstlen */
USB_GAHBCFG |= USB_GAHBCFG_INT_DMA_BURST_INCR << USB_GAHBCFG_hburstlen_bit_pos;
/* Enable DMA */
USB_GAHBCFG |= USB_GAHBCFG_dma_enable;
/* Disable HNP and SRP, not sure it's useful because we already forced dev mode */
USB_GUSBCFG &= ~(USB_GUSBCFG_SRP_cap | USB_GUSBCFG_HNP_cap);
}
void usb_drv_init(void)
{
logf("usb_drv_init");
as3525v2_connect();
logf("usb: synopsis id: %lx", USB_GSNPSID);
core_init();
}
void usb_drv_exit(void)
{
logf("usb_drv_exit");
}
int usb_drv_port_speed(void)
{
return 0;
}
int usb_drv_request_endpoint(int type, int dir)
{
(void) type;
(void) dir;
return -1;
}
void usb_drv_release_endpoint(int ep)
{
(void) ep;
}
void usb_drv_cancel_all_transfers(void)
{
}
int usb_drv_recv(int ep, void *ptr, int len)
{
(void) ep;
(void) ptr;
(void) len;
return -1;
}
int usb_drv_send(int ep, void *ptr, int len)
{
(void) ep;
(void) ptr;
(void) len;
return -1;
}
int usb_drv_send_nonblocking(int ep, void *ptr, int len)
{
(void) ep;
(void) ptr;
(void) len;
return -1;
}
/* interrupt service routine */
void INT_USB(void)
{
panicf("USB interrupt !");
}
/* (not essential? , not implemented in usb-tcc.c) */
void usb_drv_set_test_mode(int mode)
{
(void) mode;
}
void usb_drv_set_address(int address)
{
(void) address;
}
void usb_drv_stall(int ep, bool stall, bool in)
{
(void) ep;
(void) stall;
(void) in;
}
bool usb_drv_stalled(int ep, bool in)
{
(void) ep;
(void) in;
return true;
return true;
}

91
firmware/target/arm/as3525/usb-drv-as3525v2.h Normal file
View file

@ -0,0 +1,91 @@
/***************************************************************************
* __________ __ ___.
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
* \/ \/ \/ \/ \/
* $Id$
*
* Copyright © 2010 Amaury Pouly
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
* KIND, either express or implied.
*
****************************************************************************/
#ifndef __USB_DRV_AS3525v2_H__
#define __USB_DRV_AS3525v2_H__
#include "as3525v2.h"
#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
/**
* Core Global Registers
*/
#define USB_GOTGCTL (*(volatile unsigned long *)(USB_BASE + 0x000)) /** OTG Control and Status Register */
#define USB_GOTGINT (*(volatile unsigned long *)(USB_BASE + 0x004)) /** OTG Interrupt Register */
#define USB_GAHBCFG (*(volatile unsigned long *)(USB_BASE + 0x008)) /** Core AHB Configuration Register */
#define USB_GUSBCFG (*(volatile unsigned long *)(USB_BASE + 0x00C)) /** Core USB Configuration Register */
#define USB_GRSTCTL (*(volatile unsigned long *)(USB_BASE + 0x010)) /** Core Reset Register */
#define USB_GINTSTS (*(volatile unsigned long *)(USB_BASE + 0x014)) /** Core Interrupt Register */
#define USB_GINTMSK (*(volatile unsigned long *)(USB_BASE + 0x018)) /** Core Interrupt Mask Register */
#define USB_GRXSTSR (*(volatile unsigned long *)(USB_BASE + 0x01C)) /** Receive Status Debug Read Register (Read Only) */
#define USB_GRXSTSP (*(volatile unsigned long *)(USB_BASE + 0x020)) /** Receive Status Read /Pop Register (Read Only) */
#define USB_GRXFSIZ (*(volatile unsigned long *)(USB_BASE + 0x024)) /** Receive FIFO Size Register */
#define USB_GNPTXFSIZ (*(volatile unsigned long *)(USB_BASE + 0x028)) /** Periodic Transmit FIFO Size Register */
#define USB_GNPTXSTS (*(volatile unsigned long *)(USB_BASE + 0x02C)) /** Non-Periodic Transmit FIFO/Queue Status Register */
#define USB_GI2CCTL (*(volatile unsigned long *)(USB_BASE + 0x030)) /** I2C Access Register */
#define USB_GPVNDCTL (*(volatile unsigned long *)(USB_BASE + 0x034)) /** PHY Vendor Control Register */
#define USB_GGPIO (*(volatile unsigned long *)(USB_BASE + 0x038)) /** General Purpose Input/Output Register */
#define USB_GUID (*(volatile unsigned long *)(USB_BASE + 0x03C)) /** User ID Register */
#define USB_GSNPSID (*(volatile unsigned long *)(USB_BASE + 0x040)) /** Synopsys ID Register */
#define USB_GHWCFG1 (*(volatile unsigned long *)(USB_BASE + 0x044)) /** User HW Config1 Register */
#define USB_GHWCFG2 (*(volatile unsigned long *)(USB_BASE + 0x048)) /** User HW Config2 Register */
#define USB_GHWCFG3 (*(volatile unsigned long *)(USB_BASE + 0x04C)) /** User HW Config3 Register */
#define USB_GHWCFG4 (*(volatile unsigned long *)(USB_BASE + 0x050)) /** User HW Config4 Register */
#define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */
#define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
#define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
#define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */
#define USB_GHWCFG1_OUT_EP(ep) ((USB_GHWCFG1 >> ((ep) *2 + 1)) & 0x1)/** 1 if EP(ep) has out cap */
#define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */
#define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
#define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */
#define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
#define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
#define USB_GUSBCFG_SRP_cap 0x100
#define USB_GUSBCFG_HNP_cap 0x200
#define USB_GAHBCFG_hburstlen_bit_pos 1
#define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
#define USB_GAHBCFG_dma_enable (1 << 5)
/**
* Device Registers Base Addresses
*/
#define USB_DCFG (*(volatile unsigned long *)(USB_DEVICE + 0x00)) /** Device Configuration Register */
#define USB_DCTL (*(volatile unsigned long *)(USB_DEVICE + 0x04)) /** Device Control Register */
#define USB_DSTS (*(volatile unsigned long *)(USB_DEVICE + 0x08)) /** Device Status Register */
#define USB_DIEPMSK (*(volatile unsigned long *)(USB_DEVICE + 0x10)) /** Device IN Endpoint Common Interrupt Mask Register */
#define USB_DOEPMSK (*(volatile unsigned long *)(USB_DEVICE + 0x14)) /** Device OUT Endpoint Common Interrupt Mask Register */
#define USB_DAINT (*(volatile unsigned long *)(USB_DEVICE + 0x18)) /** Device All Endpoints Interrupt Register */
#define USB_DAINTMSK (*(volatile unsigned long *)(USB_DEVICE + 0x1C)) /** Device Endpoints Interrupt Mask Register */
#define USB_DTKNQR1 (*(volatile unsigned long *)(USB_DEVICE + 0x20)) /** Device IN Token Sequence Learning Queue Read Register 1 */
#define USB_DTKNQR2 (*(volatile unsigned long *)(USB_DEVICE + 0x24)) /** Device IN Token Sequence Learning Queue Register 2 */
#define USB_DTKNQP (*(volatile unsigned long *)(USB_DEVICE + 0x28)) /** Device IN Token Queue Pop register */
#define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */
#endif /* __USB_DRV_AS3525v2_H__ */