f4dcc69b51
Write the setting before enabling the PLL Fix booting problem (black screen) with Clip+ git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25415 a1c6a512-1295-4272-9138-f99709370657
385 lines
12 KiB
C
385 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "ascodec-target.h"
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#include "adc.h"
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#include "dma-target.h"
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#include "clock-target.h"
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#include "fmradio_i2c.h"
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#include "button-target.h"
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#ifndef BOOTLOADER
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#include "mmu-arm.h"
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#endif
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#include "backlight-target.h"
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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void irq_handler(void) __attribute__((interrupt ("IRQ"), naked));
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void fiq_handler(void) __attribute__((interrupt ("FIQ"), naked));
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default_interrupt(INT_WATCHDOG);
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default_interrupt(INT_TIMER1);
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default_interrupt(INT_TIMER2);
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default_interrupt(INT_USB);
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default_interrupt(INT_DMAC);
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default_interrupt(INT_NAND);
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default_interrupt(INT_IDE);
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default_interrupt(INT_MCI0);
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default_interrupt(INT_MCI1);
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default_interrupt(INT_AUDIO);
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default_interrupt(INT_SSP);
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default_interrupt(INT_I2C_MS);
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default_interrupt(INT_I2C_AUDIO);
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default_interrupt(INT_I2SIN);
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default_interrupt(INT_I2SOUT);
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default_interrupt(INT_UART);
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default_interrupt(INT_GPIOD);
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default_interrupt(RESERVED1); /* Interrupt 17 : unused */
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default_interrupt(INT_CGU);
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default_interrupt(INT_MEMORY_STICK);
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default_interrupt(INT_DBOP);
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default_interrupt(RESERVED2); /* Interrupt 21 : unused */
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default_interrupt(RESERVED3); /* Interrupt 22 : unused */
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default_interrupt(RESERVED4); /* Interrupt 23 : unused */
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default_interrupt(RESERVED5); /* Interrupt 24 : unused */
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default_interrupt(RESERVED6); /* Interrupt 25 : unused */
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default_interrupt(RESERVED7); /* Interrupt 26 : unused */
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default_interrupt(RESERVED8); /* Interrupt 27 : unused */
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default_interrupt(RESERVED9); /* Interrupt 28 : unused */
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default_interrupt(INT_GPIOA);
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default_interrupt(INT_GPIOB);
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default_interrupt(INT_GPIOC);
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static const char * const irqname[] =
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{
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"INT_WATCHDOG", "INT_TIMER1", "INT_TIMER2", "INT_USB", "INT_DMAC", "INT_NAND",
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"INT_IDE", "INT_MCI0", "INT_MCI1", "INT_AUDIO", "INT_SSP", "INT_I2C_MS",
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"INT_I2C_AUDIO", "INT_I2SIN", "INT_I2SOUT", "INT_UART", "INT_GPIOD", "RESERVED1",
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"INT_CGU", "INT_MEMORY_STICK", "INT_DBOP", "RESERVED2", "RESERVED3", "RESERVED4",
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"RESERVED5", "RESERVED6", "RESERVED7", "RESERVED8", "RESERVED9", "INT_GPIOA",
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"INT_GPIOB", "INT_GPIOC"
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};
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static void UIRQ(void)
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{
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unsigned int irq_no = 0;
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int status = VIC_IRQ_STATUS;
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if(status == 0)
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panicf("Unhandled IRQ (source unknown!)");
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while((status >>= 1))
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irq_no++;
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panicf("Unhandled IRQ %02X: %s", irq_no, irqname[irq_no]);
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}
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struct vec_int_src
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{
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int source;
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void (*isr) (void);
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};
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/* Vectored interrupts (16 available) */
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struct vec_int_src vec_int_srcs[] =
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{
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{ INT_SRC_TIMER1, INT_TIMER1 },
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{ INT_SRC_TIMER2, INT_TIMER2 },
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{ INT_SRC_DMAC, INT_DMAC },
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{ INT_SRC_NAND, INT_NAND },
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{ INT_SRC_I2C_AUDIO, INT_I2C_AUDIO },
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{ INT_SRC_AUDIO, INT_AUDIO },
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#ifdef HAVE_MULTIDRIVE
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{ INT_SRC_MCI0, INT_MCI0 },
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#endif
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#ifdef HAVE_HOTSWAP
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{ INT_SRC_GPIOA, INT_GPIOA, },
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#endif
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#ifdef HAVE_RECORDING
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{ INT_SRC_I2SIN, INT_I2SIN, },
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#endif
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};
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static void setup_vic(void)
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{
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volatile unsigned long *vic_vect_addrs = VIC_VECT_ADDRS;
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volatile unsigned long *vic_vect_cntls = VIC_VECT_CNTLS;
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const unsigned int n = sizeof(vec_int_srcs)/sizeof(vec_int_srcs[0]);
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unsigned int i;
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CGU_PERI |= CGU_VIC_CLOCK_ENABLE; /* enable VIC */
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VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
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VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
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VIC_DEF_VECT_ADDR = (unsigned long)UIRQ;
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for(i = 0; i < n; i++)
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{
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vic_vect_addrs[i] = (unsigned long)vec_int_srcs[i].isr;
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vic_vect_cntls[i] = (1<<5) | vec_int_srcs[i].source;
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}
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}
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void irq_handler(void)
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{
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asm volatile( "stmfd sp!, {r0-r5,ip,lr} \n" /* Store context */
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"ldr r5, =0xC6010030 \n" /* VIC_VECT_ADDR */
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"mov lr, pc \n" /* Return from ISR */
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"ldr pc, [r5] \n" /* execute ISR */
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"str r0, [r5] \n" /* Ack interrupt */
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"ldmfd sp!, {r0-r5,ip,lr} \n" /* Restore context */
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"subs pc, lr, #4 \n" /* Return from IRQ */
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);
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}
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void fiq_handler(void)
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{
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asm volatile (
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"subs pc, lr, #4 \r\n"
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);
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}
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#if defined(BOOTLOADER)
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static void sdram_delay(void)
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{
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int delay = 1024; /* arbitrary */
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while (delay--) ;
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}
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/* Use the same initialization than OF */
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static void sdram_init(void)
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{
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CGU_PERI |= (CGU_EXTMEM_CLOCK_ENABLE|CGU_EXTMEMIF_CLOCK_ENABLE);
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MPMC_CONTROL = 0x1; /* enable MPMC */
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MPMC_DYNAMIC_CONTROL = 0x183; /* SDRAM NOP, all clocks high */
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sdram_delay();
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MPMC_DYNAMIC_CONTROL = 0x103; /* SDRAM PALL, all clocks high */
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sdram_delay();
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MPMC_DYNAMIC_REFRESH = 0x138; /* 0x138 * 16 HCLK ticks between SDRAM refresh cycles */
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MPMC_CONFIG = 0; /* little endian, HCLK:MPMCCLKOUT[3:0] ratio = 1:1 */
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if(MPMC_PERIPH_ID2 & 0xf0)
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MPMC_DYNAMIC_READ_CONFIG = 0x1; /* command delayed, clock out not delayed */
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/* timings */
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MPMC_DYNAMIC_tRP = 2;
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MPMC_DYNAMIC_tRAS = 4;
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MPMC_DYNAMIC_tSREX = 5;
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MPMC_DYNAMIC_tAPR = 0;
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MPMC_DYNAMIC_tDAL = 4;
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MPMC_DYNAMIC_tWR = 2;
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MPMC_DYNAMIC_tRC = 5;
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MPMC_DYNAMIC_tRFC = 5;
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MPMC_DYNAMIC_tXSR = 5;
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MPMC_DYNAMIC_tRRD = 2;
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MPMC_DYNAMIC_tMRD = 2;
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#if defined(SANSA_CLIP) || defined(SANSA_M200V4) || defined(SANSA_C200V2)
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/* 16 bits external bus, low power SDRAM, 16 Mbits = 2 Mbytes */
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#define MEMORY_MODEL 0x21
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#elif defined(SANSA_E200V2) || defined(SANSA_FUZE) || defined(SANSA_CLIPV2) \
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|| defined(SANSA_CLIPPLUS) || defined(SANSA_FUZEV2)
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/* 16 bits external bus, high performance SDRAM, 64 Mbits = 8 Mbytes */
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#define MEMORY_MODEL 0x5
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#else
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#error "The external memory in your player is unknown"
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#endif
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MPMC_DYNAMIC_RASCAS_0 = (2<<8)|2; /* CAS & RAS latency = 2 clock cycles */
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MPMC_DYNAMIC_CONFIG_0 = (MEMORY_MODEL << 7);
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MPMC_DYNAMIC_RASCAS_1 = MPMC_DYNAMIC_CONFIG_1 =
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MPMC_DYNAMIC_RASCAS_2 = MPMC_DYNAMIC_CONFIG_2 =
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MPMC_DYNAMIC_RASCAS_3 = MPMC_DYNAMIC_CONFIG_3 = 0;
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MPMC_DYNAMIC_CONTROL = 0x82; /* SDRAM MODE, MPMCCLKOUT runs continuously */
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/* program the SDRAM mode register */
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/* FIXME: details the exact settings of mode register */
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asm volatile(
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"ldr r4, [%0]\n"
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: : "p"(0x30000000+0x2300*MEM) : "r4");
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MPMC_DYNAMIC_CONTROL = 0x2; /* SDRAM NORMAL, MPMCCLKOUT runs continuously */
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MPMC_DYNAMIC_CONFIG_0 |= (1<<19); /* buffer enable */
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}
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#endif /* BOOTLOADER */
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void system_init(void)
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{
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#if CONFIG_CPU == AS3525v2
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CCU_SRC = 0x57D7BF0;
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#else
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CCU_SRC = 0x1fffff0
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& ~CCU_SRC_IDE_EN; /* FIXME */
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#endif
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unsigned int reset_loops = 640;
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while(reset_loops--)
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CCU_SRL = CCU_SRL_MAGIC_NUMBER;
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CCU_SRC = CCU_SRL = 0;
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CCU_SCON = 1; /* AHB master's priority configuration :
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TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
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CGU_PERI &= ~0x7f; /* pclk 24 MHz */
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asm volatile(
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"mrc p15, 0, r0, c1, c0 \n" /* control register */
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"bic r0, r0, #3<<30 \n" /* clears bus bits : sets fastbus */
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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CGU_COUNTA = 0xff;
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CGU_PLLA = AS3525_PLLA_SETTING;
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CGU_PLLASUP = 0; /* enable PLLA */
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while(!(CGU_INTCTRL & (1<<0))); /* wait until PLLA is locked */
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#if (AS3525_MCLK_SEL == AS3525_CLK_PLLB)
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CGU_COUNTB = 0xff;
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CGU_PLLB = AS3525_PLLB_SETTING;
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CGU_PLLBSUP = 0; /* enable PLLB */
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while(!(CGU_INTCTRL & (1<<1))); /* wait until PLLB is locked */
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#endif
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/* Set FCLK frequency */
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CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
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(AS3525_FCLK_PREDIV << 2) |
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AS3525_FCLK_SEL);
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/* Set PCLK frequency */
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CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */
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(AS3525_PCLK_DIV0 << 2) |
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(AS3525_PCLK_DIV1 << 6) |
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AS3525_PCLK_SEL);
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#ifdef BOOTLOADER
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sdram_init();
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#endif /* BOOTLOADER */
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#if 0 /* the GPIO clock is already enabled by the dualboot function */
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CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
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#endif
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/* enable timer interface for TIMER1 & TIMER2 */
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CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
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setup_vic();
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dma_init();
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ascodec_init();
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#ifndef BOOTLOADER
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/* Initialize power management settings */
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ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
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#if CONFIG_TUNER
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fmradio_i2c_init();
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#endif
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#endif /* !BOOTLOADER */
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}
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void system_reboot(void)
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{
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_backlight_off();
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/* use watchdog to reset */
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CGU_PERI |= (CGU_WDOCNT_CLOCK_ENABLE | CGU_WDOIF_CLOCK_ENABLE);
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WDT_LOAD = 1; /* set counter to 1 */
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WDT_CONTROL = 3; /* enable watchdog counter & reset */
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while(1);
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}
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void system_exception_wait(void)
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{
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/* wait until button release (if a button is pressed) */
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while(button_read_device());
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/* then wait until next button press */
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while(!button_read_device());
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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#ifndef BOOTLOADER
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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void set_cpu_frequency(long frequency)
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{
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if(frequency == CPUFREQ_MAX)
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{
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#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
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/* Increasing frequency so boost voltage before change */
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ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
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/* Some players run a bit low so use 1.175 volts instead of 1.20 */
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/* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
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while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */
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#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
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asm volatile(
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"mrc p15, 0, r0, c1, c0 \n"
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#ifdef ASYNCHRONOUS_BUS
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"orr r0, r0, #3<<30 \n" /* asynchronous bus clocking */
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#else
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"bic r0, r0, #3<<30 \n" /* clear bus bits */
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"orr r0, r0, #1<<30 \n" /* synchronous bus clocking */
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#endif
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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cpu_frequency = CPUFREQ_MAX;
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}
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else
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{
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asm volatile(
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"mrc p15, 0, r0, c1, c0 \n"
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"bic r0, r0, #3<<30 \n" /* fastbus clocking */
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
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/* Decreasing frequency so reduce voltage after change */
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ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
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#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
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cpu_frequency = CPUFREQ_NORMAL;
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}
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}
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#endif /* HAVE_ADJUSTABLE_CPU_FREQ */
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#endif /* !BOOTLOADER */
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