Making this delay apply to all non-HS SD cards seems to fix some data corruption issues that came up with the switch to 4-bit widebus.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24019 a1c6a512-1295-4272-9138-f99709370657
MCI_RESPONSE_ERROR covers MCI_CMD_TIMEOUT & MCI_CMD_CRC_FAIL and makes it more clear that these are errors in the response and not the command itself.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@24003 a1c6a512-1295-4272-9138-f99709370657
Both the internal and uSD cards are now put into 4 bit widebus mode during initialization except for bootloader.
Add MCI_START_BIT_ERR to MCI_ERROR list and change name to MCI_DATA_ERROR for clarity.
Make appropriate changes to SD error codes.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23977 a1c6a512-1295-4272-9138-f99709370657
This patch changes all references/assumptions of PCLK to IDE_CLK for the internal pl180 controller.
Lower the AS3525_IDE_FREQ to 50 MHz in order to be able to divide by 2 for 25 MHz on the internal SD card.
Adjust the code in debug-as3525.c to account for the change and the frequencies reported should be correct.
Add some #if defined(HAVE_MULTIDRIVE) conditionals to cut out the code dealing with uSD for the clip.
Isolate the write delay needed for low frequency writes to only run for standard speed uSD cards. That is the only case for an MCICLK at 15.5 MHz.
Internal cards run at 25 MHz, HS uSD at 31 MHz, and standard speed uSD cards at 15.5 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23929 a1c6a512-1295-4272-9138-f99709370657
Some cards need this delay now that we're running at ident speed during this part of the init stage.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23919 a1c6a512-1295-4272-9138-f99709370657
Addition of a small write delay avoids data crc failures at lower MCICLK frequencies.
Check the actual speed value from the card's CSD register to determine HS status. HS cards can run at twice the speed of standard speed SD cards.
Internal cards & standard speed uSD now run at PCLK/4 = 15.5 MHz. HS uSD cards run at PCLK/2 = 31 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23901 a1c6a512-1295-4272-9138-f99709370657
It seems that lowering the operating frequency for the SD cards has made some uSD cards have problems with the init process.
By moving the boost from ident to operating frequency to after the switch to HS timing these card now seem to init normally.
We still need to fix the problem where the internal cards and non HS uSD cards are still slightly overclocked at 31 MHz.
As of now we experience data crc failures during writes at the next lower frequency of 15.5 MHz.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23870 a1c6a512-1295-4272-9138-f99709370657
This is within the SD Spec for v2 High Speed cards but still over the 25 MHz limit for v1 and non-HS v2 cards.
Test_disk write & verify passes on both internal and uSD.
The v1 cards still need to be lowered to 15 MHz but that causes data crc failures at this point.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23835 a1c6a512-1295-4272-9138-f99709370657
Currently the bypass bit is not cleared so it's possible to enter the identification phase at bypass speed instead of ident speed.
The simplest solution to ensure the bypass bit is not set is to set the register with an = operation instead of |=.
This makes setting the MCI_CLOCK register at the end of the controller init unnecessary.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23830 a1c6a512-1295-4272-9138-f99709370657
bits 13:0 must not be modified (except for bit 8 ?)
fixes FM on my Clipv1 (some Clips weren't affected)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23826 a1c6a512-1295-4272-9138-f99709370657
If the controllers were already enabled there was a chance we could try to read the MCI_CLOCK registers while the cards were buffering and then disable the controllers prematurely.
I guess funman knows and sees all!! Thanks funman.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23811 a1c6a512-1295-4272-9138-f99709370657
Because we turn off the clocks to the SD controllers between disk accesses we were unable to read the MCI_CLOCK registers until there was a disk access. Now we can read them immediately.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23810 a1c6a512-1295-4272-9138-f99709370657
Enabling/disabling of the NAF and IDE clocks is now grouped together as both are related to the internal SD.
Sequence for disabling SD now mirrors the enable sequence.
Comments added to make it easier to follow the configuration change for XPD from gpio to mci-sd and back.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23808 a1c6a512-1295-4272-9138-f99709370657
- Use the fact that unicode code currently does not support chars above 0xffff
(see utf8decode()), and change diacritic database's char code type to
unsigned short from int. Also comment out database entries above unsupported
range.
- Use const when possible.
- Iterate over buffer using the buffer's pointer, thus avoiding usage of some
variables, and avoiding multiple access to the same array item.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23776 a1c6a512-1295-4272-9138-f99709370657
- Fix bug which cause wrong placement of characters in some specific conditions
- Fix multiple similar entries in cache
- Protect against negative x values passed to drawing function
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23765 a1c6a512-1295-4272-9138-f99709370657
We had 3 different references to the same value. Rockbox always uses a blocksize of 512 bytes for SD and we were using SECTOR_SIZE, SD_BLOCK_SIZE, & card_info[drive].blocksize to use this value. Now the only reference being used is SD_BLOCK_SIZE.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23746 a1c6a512-1295-4272-9138-f99709370657
This commit corrects the display of diacritic characters, which exist in many
languages. Hopefully, it will make Rockbox much more usable for users of these
languages.
Diacritic information (which used to decide whether a given character is
diacritic or not) is taken from the Unicode Standard, Version 5.2.
This feature does not affect drawing performance much, as the diacritic
database is cached (simple MRU mechanism).
There may be room for further performance, footprint, and
code-reuse wise improvements, that could be worked on in the future.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23742 a1c6a512-1295-4272-9138-f99709370657
Patch by Boris Gjenero (dreamlayers). Writes are retried on failure now so this should be safe.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23741 a1c6a512-1295-4272-9138-f99709370657
Writes will now be retried if they fail, and will be done using multisector transfers which should be faster.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23740 a1c6a512-1295-4272-9138-f99709370657
Flyspray: FS#10371
Authors: Fred Bauer and myself
Only enabled on e200v2 and Fuze (crashes on clipv1)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23739 a1c6a512-1295-4272-9138-f99709370657
When read it returns all enabled interrupt sources
When written it enables interrupt sources for each bit set
So just like VIC_INT_EN_CLEAR, we don't have to read the previous value
before writing to it (VIC_INT_EN_CLEAR is write-only anyway)
Thanks to Fred Bauer for spotting
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23734 a1c6a512-1295-4272-9138-f99709370657
We don't need to check the FIFO for MCI_RX_ACTIVE because we don't experience problems reading from the SD cards.
We need the MCI_TX_ACTIVE FIFO check during writes because some SD cards spend longer times in the PRG state
programming the data that has been written to them.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23733 a1c6a512-1295-4272-9138-f99709370657
We use wait_for_state() before any command that requires a state prior to being sent. Waiting after a transfer is not needed.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23732 a1c6a512-1295-4272-9138-f99709370657
of the CH_CONTROL and CH_CONFIGURATION registers easier to follow.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23725 a1c6a512-1295-4272-9138-f99709370657
The crc check on responses to sd commands was being bypassed due to a SD_APP_OP_COND special case. Now a short response is returned
even if the crc check fails so we can check the busy bit. The send_cmd() function still returns a false value but it loads the response
variable with the cmd response.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23718 a1c6a512-1295-4272-9138-f99709370657
- two essential parts of Sansa AMS drivers are optimzed away in newer gcc, so mark them volatile.
- use "r" instead of "i" (which is apparently invalid syntax) for the input list in some inline assembly
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23634 a1c6a512-1295-4272-9138-f99709370657
* Remember last used text input mode (keyboard or morse input) in settings.
* Add setting "Use Morse Code Input" under Settings -> General Settings -> System.
Now it is possible for some of targets without button combo for changing input mode to use morse input by changing the setting. it's not possible for them to change input mode during in the keyboard screen of course.
There are still targets without morse input mode.
Flyspray: FS#10338
Author: myself, David Johnston
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23567 a1c6a512-1295-4272-9138-f99709370657
Patch by Boris Gjenero. Displays the current flowing into or out of the
battery on the ipodvideo. Other ipods do not appear to have this ADC channel
connected.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23500 a1c6a512-1295-4272-9138-f99709370657
Init CGU_AUDIO with correct clock source (for play & rec)
Do not disable recording clocks when starting playback, they are already disabled
Move clock enable/disable code from dma callback to init
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23493 a1c6a512-1295-4272-9138-f99709370657
If a panicf() is called while a button is still pressed, the Sansa would
reboot immediately with no chance to see the message
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23490 a1c6a512-1295-4272-9138-f99709370657
INT_GPIOB is not used
INT_MCI0 and INT_GPIOA are only put in the table if needed
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23481 a1c6a512-1295-4272-9138-f99709370657
Unaligned memory ops will cause a data abort anyway
Make the check for samplerate at buildtime
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23480 a1c6a512-1295-4272-9138-f99709370657
Still disabled on all targets:
- Fuze and e200v2 see spurious interrupts with no source defined
- Clip/m200v4 deadlock instantly when starting recording (perhaps due to low memory size)
Having the code in SVN will make working on this feature easier
Also add keymaps for Fuze, and correct Frequency section of recording
options : the 22.05kHz limitation of e200v1 and c200v1 doesn't apply to
Sansa AMS (different I2S hardware, unrelated to as3514)
Flyspray: FS#10371
Authors: Fred Bauer and myself
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23476 a1c6a512-1295-4272-9138-f99709370657
Also fix a typo that erroneously enabled button_hold in button-target.h
Flyspray: FS#10732
Author: Yann Muller
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23383 a1c6a512-1295-4272-9138-f99709370657
