as3525v2-usb: simplify register definitions
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26969 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Amaury Pouly
parent
1ef8cd769d
commit
b5266ce3e5
1 changed files with 53 additions and 49 deletions
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@ -25,34 +25,36 @@
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#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
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#define USB_BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
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/**
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* Core Global Registers
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*/
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#define USB_GOTGCTL (*(volatile unsigned long *)(USB_BASE + 0x000)) /** OTG Control and Status Register */
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#define USB_GOTGINT (*(volatile unsigned long *)(USB_BASE + 0x004)) /** OTG Interrupt Register */
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#define USB_GAHBCFG (*(volatile unsigned long *)(USB_BASE + 0x008)) /** Core AHB Configuration Register */
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#define USB_GUSBCFG (*(volatile unsigned long *)(USB_BASE + 0x00C)) /** Core USB Configuration Register */
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#define USB_GRSTCTL (*(volatile unsigned long *)(USB_BASE + 0x010)) /** Core Reset Register */
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#define USB_GINTSTS (*(volatile unsigned long *)(USB_BASE + 0x014)) /** Core Interrupt Register */
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#define USB_GINTMSK (*(volatile unsigned long *)(USB_BASE + 0x018)) /** Core Interrupt Mask Register */
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#define USB_GRXSTSR (*(volatile unsigned long *)(USB_BASE + 0x01C)) /** Receive Status Debug Read Register (Read Only) */
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#define USB_GRXSTSP (*(volatile unsigned long *)(USB_BASE + 0x020)) /** Receive Status Read /Pop Register (Read Only) */
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#define USB_GRXFSIZ (*(volatile unsigned long *)(USB_BASE + 0x024)) /** Receive FIFO Size Register */
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#define USB_GNPTXFSIZ (*(volatile unsigned long *)(USB_BASE + 0x028)) /** Periodic Transmit FIFO Size Register */
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#define USB_GNPTXSTS (*(volatile unsigned long *)(USB_BASE + 0x02C)) /** Non-Periodic Transmit FIFO/Queue Status Register */
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#define USB_GI2CCTL (*(volatile unsigned long *)(USB_BASE + 0x030)) /** I2C Access Register */
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#define USB_GPVNDCTL (*(volatile unsigned long *)(USB_BASE + 0x034)) /** PHY Vendor Control Register */
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#define USB_GGPIO (*(volatile unsigned long *)(USB_BASE + 0x038)) /** General Purpose Input/Output Register */
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#define USB_GUID (*(volatile unsigned long *)(USB_BASE + 0x03C)) /** User ID Register */
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#define USB_GSNPSID (*(volatile unsigned long *)(USB_BASE + 0x040)) /** Synopsys ID Register */
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#define USB_GHWCFG1 (*(volatile unsigned long *)(USB_BASE + 0x044)) /** User HW Config1 Register */
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#define USB_GHWCFG2 (*(volatile unsigned long *)(USB_BASE + 0x048)) /** User HW Config2 Register */
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#define USB_GHWCFG3 (*(volatile unsigned long *)(USB_BASE + 0x04C)) /** User HW Config3 Register */
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#define USB_GHWCFG4 (*(volatile unsigned long *)(USB_BASE + 0x050)) /** User HW Config4 Register */
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#define USB_GOTGCTL USB_BASE_REG(0x000) /** OTG Control and Status Register */
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#define USB_GOTGINT USB_BASE_REG(0x004) /** OTG Interrupt Register */
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#define USB_GAHBCFG USB_BASE_REG(0x008) /** Core AHB Configuration Register */
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#define USB_GUSBCFG USB_BASE_REG(0x00C) /** Core USB Configuration Register */
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#define USB_GRSTCTL USB_BASE_REG(0x010) /** Core Reset Register */
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#define USB_GINTSTS USB_BASE_REG(0x014) /** Core Interrupt Register */
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#define USB_GINTMSK USB_BASE_REG(0x018) /** Core Interrupt Mask Register */
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#define USB_GRXSTSR USB_BASE_REG(0x01C) /** Receive Status Debug Read Register (Read Only) */
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#define USB_GRXSTSP USB_BASE_REG(0x020) /** Receive Status Read /Pop Register (Read Only) */
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#define USB_GRXFSIZ USB_BASE_REG(0x024) /** Receive FIFO Size Register */
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#define USB_GNPTXFSIZ USB_BASE_REG(0x028) /** Periodic Transmit FIFO Size Register */
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#define USB_GNPTXSTS USB_BASE_REG(0x02C) /** Non-Periodic Transmit FIFO/Queue Status Register */
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#define USB_GI2CCTL USB_BASE_REG(0x030) /** I2C Access Register */
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#define USB_GPVNDCTL USB_BASE_REG(0x034) /** PHY Vendor Control Register */
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#define USB_GGPIO USB_BASE_REG(0x038) /** General Purpose Input/Output Register */
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#define USB_GUID USB_BASE_REG(0x03C) /** User ID Register */
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#define USB_GSNPSID USB_BASE_REG(0x040) /** Synopsys ID Register */
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#define USB_GHWCFG1 USB_BASE_REG(0x044) /** User HW Config1 Register */
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#define USB_GHWCFG2 USB_BASE_REG(0x048) /** User HW Config2 Register */
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#define USB_GHWCFG3 USB_BASE_REG(0x04C) /** User HW Config3 Register */
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#define USB_GHWCFG4 USB_BASE_REG(0x050) /** User HW Config4 Register */
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/* 1<=ep<=15, don't use ep=0 !!! */
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/** Device IN Endpoint Transmit FIFO (ep) Size Register */
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#define USB_DIEPTXFSIZ(ep) (*(volatile unsigned long *)(USB_BASE + 0x100 + 4 * (ep)))
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#define USB_DIEPTXFSIZ(ep) USB_BASE_REG(0x100 + 4 * (ep))
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/** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/
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#define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \
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@ -161,24 +163,26 @@
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/**
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* Device Registers Base Addresses
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*/
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#define USB_DCFG (*(volatile unsigned long *)(USB_DEVICE + 0x00)) /** Device Configuration Register */
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#define USB_DCTL (*(volatile unsigned long *)(USB_DEVICE + 0x04)) /** Device Control Register */
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#define USB_DSTS (*(volatile unsigned long *)(USB_DEVICE + 0x08)) /** Device Status Register */
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#define USB_DIEPMSK (*(volatile unsigned long *)(USB_DEVICE + 0x10)) /** Device IN Endpoint Common Interrupt Mask Register */
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#define USB_DOEPMSK (*(volatile unsigned long *)(USB_DEVICE + 0x14)) /** Device OUT Endpoint Common Interrupt Mask Register */
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#define USB_DAINT (*(volatile unsigned long *)(USB_DEVICE + 0x18)) /** Device All Endpoints Interrupt Register */
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#define USB_DAINTMSK (*(volatile unsigned long *)(USB_DEVICE + 0x1C)) /** Device Endpoints Interrupt Mask Register */
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#define USB_DTKNQR1 (*(volatile unsigned long *)(USB_DEVICE + 0x20)) /** Device IN Token Sequence Learning Queue Read Register 1 */
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#define USB_DTKNQR2 (*(volatile unsigned long *)(USB_DEVICE + 0x24)) /** Device IN Token Sequence Learning Queue Register 2 */
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#define USB_DTKNQP (*(volatile unsigned long *)(USB_DEVICE + 0x28)) /** Device IN Token Queue Pop register */
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#define USB_DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
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#define USB_DCFG USB_DEV_REG(0x00) /** Device Configuration Register */
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#define USB_DCTL USB_DEV_REG(0x04) /** Device Control Register */
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#define USB_DSTS USB_DEV_REG(0x08) /** Device Status Register */
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#define USB_DIEPMSK USB_DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */
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#define USB_DOEPMSK USB_DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */
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#define USB_DAINT USB_DEV_REG(0x18) /** Device All Endpoints Interrupt Register */
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#define USB_DAINTMSK USB_DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */
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#define USB_DTKNQR1 USB_DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */
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#define USB_DTKNQR2 USB_DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */
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#define USB_DTKNQP USB_DEV_REG(0x28) /** Device IN Token Queue Pop register */
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/* fixme: those registers are not present in usb_registers.h but are in dwc_otgh_regs.h.
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* the previous registers exists but has a different name :( */
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#define USB_DVBUSDIS (*(volatile unsigned long *)(USB_DEVICE + 0x28)) /** Device VBUS discharge register*/
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#define USB_DVBUSPULSE (*(volatile unsigned long *)(USB_DEVICE + 0x2C)) /** Device VBUS pulse register */
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#define USB_DTKNQR3 (*(volatile unsigned long *)(USB_DEVICE + 0x30)) /** Device IN Token Queue Read Register 3 (RO) */
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#define USB_DTHRCTL (*(volatile unsigned long *)(USB_DEVICE + 0x30)) /** Device Thresholding control register */
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#define USB_DTKNQR4 (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN Token Queue Read Register 4 (RO) */
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#define USB_FFEMPTYMSK (*(volatile unsigned long *)(USB_DEVICE + 0x34)) /** Device IN EPs empty Inr. Mask Register */
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#define USB_DVBUSDIS USB_DEV_REG(0x28) /** Device VBUS discharge register*/
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#define USB_DVBUSPULSE USB_DEV_REG(0x2C) /** Device VBUS pulse register */
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#define USB_DTKNQR3 USB_DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */
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#define USB_DTHRCTL USB_DEV_REG(0x30) /** Device Thresholding control register */
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#define USB_DTKNQR4 USB_DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */
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#define USB_FFEMPTYMSK USB_DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */
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#define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
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#define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
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@ -227,15 +231,15 @@
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/* 0<=ep<=15, you can use ep=0 */
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/** Device IN Endpoint (ep) Control Register */
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#define USB_DIEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20))
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#define USB_DIEPCTL(ep) USB_DEV_REG(0x100 + (ep) * 0x20)
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/** Device IN Endpoint (ep) Interrupt Register */
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#define USB_DIEPINT(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x8))
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#define USB_DIEPINT(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x8)
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/** Device IN Endpoint (ep) Transfer Size Register */
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#define USB_DIEPTSIZ(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x10))
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#define USB_DIEPTSIZ(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x10)
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/** Device IN Endpoint (ep) DMA Address Register */
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#define USB_DIEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x14))
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#define USB_DIEPDMA(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x14)
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/** Device IN Endpoint (ep) Transmit FIFO Status Register */
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#define USB_DTXFSTS(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x100 + (ep) * 0x20 + 0x18))
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#define USB_DTXFSTS(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x18)
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/* the following also apply to DIEPMSK */
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#define USB_DIEPINT_xfercompl (1 << 0) /** Transfer complete */
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@ -256,17 +260,17 @@
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/* 0<=ep<=15, you can use ep=0 */
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/** Device OUT Endpoint (ep) Control Register */
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#define USB_DOEPCTL(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20))
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#define USB_DOEPCTL(ep) USB_DEV_REG(0x300 + (ep) * 0x20)
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/** Device OUT Endpoint (ep) Frame number Register */
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#define USB_DOEPFN(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x4))
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#define USB_DOEPFN(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x4)
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/** Device Endpoint (ep) Interrupt Register */
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#define USB_DOEPINT(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x8))
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#define USB_DOEPINT(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x8)
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/** Device OUT Endpoint (ep) Transfer Size Register */
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#define USB_DOEPTSIZ(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x10))
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#define USB_DOEPTSIZ(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x10)
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/** Device Endpoint (ep) DMA Address Register */
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#define USB_DOEPDMA(ep) (*(volatile unsigned long *)(USB_DEVICE + 0x300 + (ep) * 0x20 + 0x14))
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#define USB_DOEPDMA(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x14)
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#define USB_PCGCCTL (*(volatile unsigned long *)(USB_BASE + 0xE00)) /** Power and Clock Gating Control Register */
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#define USB_PCGCCTL USB_BASE_REG(0xE00) /** Power and Clock Gating Control Register */
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/** Maximum Packet Size
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