b5266ce3e5
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26969 a1c6a512-1295-4272-9138-f99709370657
395 lines
20 KiB
C
395 lines
20 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2010 Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __USB_DRV_AS3525v2_H__
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#define __USB_DRV_AS3525v2_H__
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#include "as3525v2.h"
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#define USB_DEVICE (USB_BASE + 0x0800) /** USB Device base address */
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#define USB_BASE_REG(offset) (*(volatile unsigned long *)(USB_BASE + offset))
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/**
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* Core Global Registers
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*/
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#define USB_GOTGCTL USB_BASE_REG(0x000) /** OTG Control and Status Register */
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#define USB_GOTGINT USB_BASE_REG(0x004) /** OTG Interrupt Register */
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#define USB_GAHBCFG USB_BASE_REG(0x008) /** Core AHB Configuration Register */
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#define USB_GUSBCFG USB_BASE_REG(0x00C) /** Core USB Configuration Register */
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#define USB_GRSTCTL USB_BASE_REG(0x010) /** Core Reset Register */
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#define USB_GINTSTS USB_BASE_REG(0x014) /** Core Interrupt Register */
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#define USB_GINTMSK USB_BASE_REG(0x018) /** Core Interrupt Mask Register */
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#define USB_GRXSTSR USB_BASE_REG(0x01C) /** Receive Status Debug Read Register (Read Only) */
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#define USB_GRXSTSP USB_BASE_REG(0x020) /** Receive Status Read /Pop Register (Read Only) */
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#define USB_GRXFSIZ USB_BASE_REG(0x024) /** Receive FIFO Size Register */
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#define USB_GNPTXFSIZ USB_BASE_REG(0x028) /** Periodic Transmit FIFO Size Register */
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#define USB_GNPTXSTS USB_BASE_REG(0x02C) /** Non-Periodic Transmit FIFO/Queue Status Register */
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#define USB_GI2CCTL USB_BASE_REG(0x030) /** I2C Access Register */
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#define USB_GPVNDCTL USB_BASE_REG(0x034) /** PHY Vendor Control Register */
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#define USB_GGPIO USB_BASE_REG(0x038) /** General Purpose Input/Output Register */
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#define USB_GUID USB_BASE_REG(0x03C) /** User ID Register */
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#define USB_GSNPSID USB_BASE_REG(0x040) /** Synopsys ID Register */
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#define USB_GHWCFG1 USB_BASE_REG(0x044) /** User HW Config1 Register */
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#define USB_GHWCFG2 USB_BASE_REG(0x048) /** User HW Config2 Register */
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#define USB_GHWCFG3 USB_BASE_REG(0x04C) /** User HW Config3 Register */
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#define USB_GHWCFG4 USB_BASE_REG(0x050) /** User HW Config4 Register */
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/* 1<=ep<=15, don't use ep=0 !!! */
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/** Device IN Endpoint Transmit FIFO (ep) Size Register */
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#define USB_DIEPTXFSIZ(ep) USB_BASE_REG(0x100 + 4 * (ep))
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/** Build the content of a FIFO size register like USB_DIEPTXFSIZ(i) and USB_GNPTXFSIZ*/
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#define USB_MAKE_FIFOSIZE_DATA(startadr, depth) \
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(((startadr) & 0xffff) | ((depth) << 16))
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/** Retrieve fifo size for such registers */
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#define USB_GET_FIFOSIZE_DEPTH(data) \
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((data) >> 16)
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/** Retrieve fifo start address for such registers */
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#define USB_GET_FIFOSIZE_START_ADR(data) \
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((data) & 0xffff)
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#define USB_GRSTCTL_csftrst (1 << 0) /** Core soft reset */
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#define USB_GRSTCTL_hsftrst (1 << 1) /** Hclk soft reset */
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#define USB_GRSTCTL_intknqflsh (1 << 3) /** In Token Sequence Learning Queue Flush */
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#define USB_GRSTCTL_rxfflsh_flush (1 << 4) /** RxFIFO Flush */
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#define USB_GRSTCTL_txfflsh_flush (1 << 5) /** TxFIFO Flush */
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#define USB_GRSTCTL_txfnum_bit_pos 6 /** TxFIFO Number */
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#define USB_GRSTCTL_txfnum_bits (0x1f << 6)
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#define USB_GRSTCTL_ahbidle (1 << 31) /** AHB idle state*/
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#define USB_GHWCFG1_IN_EP(ep) ((USB_GHWCFG1 >> ((ep) *2)) & 0x1) /** 1 if EP(ep) has in cap */
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#define USB_GHWCFG1_OUT_EP(ep) ((USB_GHWCFG1 >> ((ep) *2 + 1)) & 0x1)/** 1 if EP(ep) has out cap */
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#define USB_GHWCFG2_ARCH ((USB_GHWCFG2 >> 3) & 0x3) /** Architecture */
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#define USB_GHWCFG2_HS_PHY_TYPE ((USB_GHWCFG2 >> 6) & 0x3) /** High speed PHY type */
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#define USB_GHWCFG2_FS_PHY_TYPE ((USB_GHWCFG2 >> 8) & 0x3) /** Full speed PHY type */
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#define USB_GHWCFG2_NUM_EP ((USB_GHWCFG2 >> 10) & 0xf) /** Number of endpoints */
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#define USB_GHWCFG2_DYN_FIFO ((USB_GHWCFG2 >> 19) & 0x1) /** Dynamic FIFO */
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/* For USB_GHWCFG2_HS_PHY_TYPE and USB_GHWCFG2_SS_PHY_TYPE */
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#define USB_PHY_TYPE_UNSUPPORTED 0
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#define USB_PHY_TYPE_UTMI 1
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#define USB_INT_DMA_ARCH 2
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#define USB_GHWCFG3_DFIFO_LEN (USB_GHWCFG3 >> 16) /** Total fifo size */
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#define USB_GHWCFG4_UTMI_PHY_DATA_WIDTH ((USB_GHWCFG4 >> 14) & 0x3) /** UTMI+ data bus width (format is unsure) */
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#define USB_GHWCFG4_DED_FIFO_EN ((USB_GHWCFG4 >> 25) & 0x1) /** Dedicated Tx FIFOs */
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#define USB_GHWCFG4_NUM_IN_EP ((USB_GHWCFG4 >> 26) & 0xf) /** Number of IN endpoints */
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#define USB_GUSBCFG_toutcal_bit_pos 0
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#define USB_GUSBCFG_toutcal_bits (0x7 << USB_GUSBCFG_toutcal_bit_pos)
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#define USB_GUSBCFG_phy_if (1 << 3) /** select utmi bus width ? */
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#define USB_GUSBCFG_ulpi_utmi_sel (1 << 4) /** select ulpi:1 or utmi:0 */
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#define USB_GUSBCFG_fsintf (1 << 5)
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#define USB_GUSBCFG_physel (1 << 6)
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#define USB_GUSBCFG_ddrsel (1 << 7)
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#define USB_GUSBCFG_srpcap (1 << 8)
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#define USB_GUSBCFG_hnpcapp (1 << 9)
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#define USB_GUSBCFG_usbtrdtim_bit_pos 10
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#define USB_GUSBCFG_usbtrdtim_bits (0xf << USB_GUSBCFG_usbtrdtim_bit_pos)
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#define USB_GUSBCFG_nptxfrwnden (1 << 14)
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#define USB_GUSBCFG_phylpwrclksel (1 << 15)
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#define USB_GUSBCFG_otgutmifssel (1 << 16)
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#define USB_GUSBCFG_ulpi_fsls (1 << 17)
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#define USB_GUSBCFG_ulpi_auto_res (1 << 18)
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#define USB_GUSBCFG_ulpi_clk_sus_m (1 << 19)
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#define USB_GUSBCFG_ulpi_ext_vbus_drv (1 << 20)
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#define USB_GUSBCFG_ulpi_int_vbus_indicator (1 << 21)
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#define USB_GUSBCFG_term_sel_dl_pulse (1 << 22)
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#define USB_GUSBCFG_force_host_mode (1 << 29)
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#define USB_GUSBCFG_force_device_mode (1 << 30)
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#define USB_GUSBCFG_corrupt_tx_packet (1 << 31)
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#define USB_GAHBCFG_glblintrmsk (1 << 0) /** Global interrupt mask */
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#define USB_GAHBCFG_hburstlen_bit_pos 1
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#define USB_GAHBCFG_INT_DMA_BURST_SINGLE 0
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#define USB_GAHBCFG_INT_DMA_BURST_INCR 1 /** note: the linux patch has several other value, this is one picked for internal dma */
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#define USB_GAHBCFG_INT_DMA_BURST_INCR4 3
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#define USB_GAHBCFG_INT_DMA_BURST_INCR8 5
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#define USB_GAHBCFG_INT_DMA_BURST_INCR16 7
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#define USB_GAHBCFG_dma_enable (1 << 5) /** Enable DMA */
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/* NOTE: USB_GINTSTS bits are the same as in USB_GINTMSK plus the following one */
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#define USB_GINTSTS_curmode (1 << 0) /** Current mode: 1 for host, 0 for device */
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#define USB_GINTMSK_modemismatch (1 << 1) /** mode mismatch ? */
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#define USB_GINTMSK_otgintr (1 << 2)
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#define USB_GINTMSK_sofintr (1 << 3)
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#define USB_GINTMSK_rxstsqlvl (1 << 4)
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#define USB_GINTMSK_nptxfempty (1 << 5) /** Non-periodic TX fifo empty ? */
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#define USB_GINTMSK_ginnakeff (1 << 6)
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#define USB_GINTMSK_goutnakeff (1 << 7)
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#define USB_GINTMSK_i2cintr (1 << 9)
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#define USB_GINTMSK_erlysuspend (1 << 10)
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#define USB_GINTMSK_usbsuspend (1 << 11) /** USB suspend */
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#define USB_GINTMSK_usbreset (1 << 12) /** USB reset */
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#define USB_GINTMSK_enumdone (1 << 13) /** Enumeration done */
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#define USB_GINTMSK_isooutdrop (1 << 14)
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#define USB_GINTMSK_eopframe (1 << 15)
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#define USB_GINTMSK_epmismatch (1 << 17) /** endpoint mismatch ? */
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#define USB_GINTMSK_inepintr (1 << 18) /** in pending ? */
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#define USB_GINTMSK_outepintr (1 << 19) /** out pending ? */
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#define USB_GINTMSK_incomplisoin (1 << 20) /** ISP in complete ? */
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#define USB_GINTMSK_incomplisoout (1 << 21) /** ISO out complete ? */
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#define USB_GINTMSK_portintr (1 << 24) /** Port status change ? */
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#define USB_GINTMSK_hcintr (1 << 25)
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#define USB_GINTMSK_ptxfempty (1 << 26) /** Periodic TX fifof empty ? */
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#define USB_GINTMSK_conidstschng (1 << 28)
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#define USB_GINTMSK_disconnect (1 << 29) /** Disconnect */
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#define USB_GINTMSK_sessreqintr (1 << 30) /** Session request */
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#define USB_GINTMSK_wkupintr (1 << 31) /** Wake up */
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/**
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* Device Registers Base Addresses
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*/
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#define USB_DEV_REG(offset) (*(volatile unsigned long *)(USB_DEVICE + offset))
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#define USB_DCFG USB_DEV_REG(0x00) /** Device Configuration Register */
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#define USB_DCTL USB_DEV_REG(0x04) /** Device Control Register */
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#define USB_DSTS USB_DEV_REG(0x08) /** Device Status Register */
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#define USB_DIEPMSK USB_DEV_REG(0x10) /** Device IN Endpoint Common Interrupt Mask Register */
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#define USB_DOEPMSK USB_DEV_REG(0x14) /** Device OUT Endpoint Common Interrupt Mask Register */
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#define USB_DAINT USB_DEV_REG(0x18) /** Device All Endpoints Interrupt Register */
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#define USB_DAINTMSK USB_DEV_REG(0x1C) /** Device Endpoints Interrupt Mask Register */
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#define USB_DTKNQR1 USB_DEV_REG(0x20) /** Device IN Token Sequence Learning Queue Read Register 1 */
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#define USB_DTKNQR2 USB_DEV_REG(0x24) /** Device IN Token Sequence Learning Queue Register 2 */
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#define USB_DTKNQP USB_DEV_REG(0x28) /** Device IN Token Queue Pop register */
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/* fixme: those registers are not present in usb_registers.h but are in dwc_otgh_regs.h.
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* the previous registers exists but has a different name :( */
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#define USB_DVBUSDIS USB_DEV_REG(0x28) /** Device VBUS discharge register*/
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#define USB_DVBUSPULSE USB_DEV_REG(0x2C) /** Device VBUS pulse register */
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#define USB_DTKNQR3 USB_DEV_REG(0x30) /** Device IN Token Queue Read Register 3 (RO) */
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#define USB_DTHRCTL USB_DEV_REG(0x30) /** Device Thresholding control register */
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#define USB_DTKNQR4 USB_DEV_REG(0x34) /** Device IN Token Queue Read Register 4 (RO) */
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#define USB_FFEMPTYMSK USB_DEV_REG(0x34) /** Device IN EPs empty Inr. Mask Register */
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#define USB_DCTL_rmtwkupsig (1 << 0) /** Remote Wakeup */
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#define USB_DCTL_sftdiscon (1 << 1) /** Soft Disconnect */
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#define USB_DCTL_gnpinnaksts (1 << 2) /** Global Non-Periodic IN NAK Status */
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#define USB_DCTL_goutnaksts (1 << 3) /** Global OUT NAK Status */
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#define USB_DCTL_tstctl_bit_pos 4 /** Test Control */
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#define USB_DCTL_tstctl_bits (0x7 << USB_DCTL_tstctl_bit_pos)
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#define USB_DCTL_sgnpinnak (1 << 7) /** Set Global Non-Periodic IN NAK */
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#define USB_DCTL_cgnpinnak (1 << 8) /** Clear Global Non-Periodic IN NAK */
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#define USB_DCTL_sgoutnak (1 << 9) /** Set Global OUT NAK */
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#define USB_DCTL_cgoutnak (1 << 10) /** Clear Global OUT NAK */
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/* "documented" in usb_constants.h only */
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#define USB_DCTL_pwronprgdone (1 << 11) /** Power on Program Done ? */
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#define USB_DCFG_devspd_bits 0x3 /** Device Speed */
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#define USB_DCFG_devspd_hs_phy_hs 0 /** High speed PHY running at high speed */
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#define USB_DCFG_devspd_hs_phy_fs 1 /** High speed PHY running at full speed */
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#define USB_DCFG_nzstsouthshk (1 << 2) /** Non Zero Length Status OUT Handshake */
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#define USB_DCFG_devadr_bit_pos 4 /** Device Address */
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#define USB_DCFG_devadr_bits (0x7f << USB_DCFG_devadr_bit_pos)
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#define USB_DCFG_perfrint_bit_pos 11 /** Periodic Frame Interval */
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#define USB_DCFG_perfrint_bits (0x3 << USB_DCFG_perfrint_bit_pos)
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#define USB_DCFG_FRAME_INTERVAL_80 0
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#define USB_DCFG_FRAME_INTERVAL_85 1
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#define USB_DCFG_FRAME_INTERVAL_90 2
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#define USB_DCFG_FRAME_INTERVAL_95 3
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#define USB_DSTS_suspsts (1 << 0) /** Suspend status */
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#define USB_DSTS_enumspd_bit_pos 1 /** Enumerated speed */
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#define USB_DSTS_enumspd_bits (0x3 << USB_DSTS_enumspd_bit_pos)
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#define USB_DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ 0
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#define USB_DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ 1
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#define USB_DSTS_ENUMSPD_LS_PHY_6MHZ 2
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#define USB_DSTS_ENUMSPD_FS_PHY_48MHZ 3
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#define USB_DSTS_errticerr (1 << 3) /** Erratic errors ? */
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#define USB_DSTS_soffn_bit_pos 7 /** Frame or Microframe Number of the received SOF */
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#define USB_DSTS_soffn_bits (0x3fff << USB_DSTS_soffn_bit_pos)
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#define USB_DTHRCTL_non_iso_thr_en (1 << 0)
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#define USB_DTHRCTL_iso_thr_en (1 << 1)
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#define USB_DTHRCTL_tx_thr_len_bit_pos 2
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#define USB_DTHRCTL_tx_thr_len_bits (0x1FF << USB_DTHRCTL_tx_thr_len_bit_pos)
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#define USB_DTHRCTL_rx_thr_en (1 << 16)
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#define USB_DTHRCTL_rx_thr_len_bit_pos 17
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#define USB_DTHRCTL_rx_thr_len_bits (0x1FF << USB_DTHRCTL_rx_thr_len_bit_pos)
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/* 0<=ep<=15, you can use ep=0 */
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/** Device IN Endpoint (ep) Control Register */
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#define USB_DIEPCTL(ep) USB_DEV_REG(0x100 + (ep) * 0x20)
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/** Device IN Endpoint (ep) Interrupt Register */
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#define USB_DIEPINT(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x8)
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/** Device IN Endpoint (ep) Transfer Size Register */
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#define USB_DIEPTSIZ(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x10)
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/** Device IN Endpoint (ep) DMA Address Register */
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#define USB_DIEPDMA(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x14)
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/** Device IN Endpoint (ep) Transmit FIFO Status Register */
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#define USB_DTXFSTS(ep) USB_DEV_REG(0x100 + (ep) * 0x20 + 0x18)
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/* the following also apply to DIEPMSK */
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#define USB_DIEPINT_xfercompl (1 << 0) /** Transfer complete */
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#define USB_DIEPINT_epdisabled (1 << 1) /** Endpoint disabled */
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#define USB_DIEPINT_ahberr (1 << 2) /** AHB error */
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#define USB_DIEPINT_timeout (1 << 3) /** Timeout handshake (non-iso TX) */
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#define USB_DIEPINT_intktxfemp (1 << 4) /** IN token received with tx fifo empty */
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#define USB_DIEPINT_intknepmis (1 << 5) /** IN token received with ep mismatch */
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#define USB_DIEPINT_inepnakeff (1 << 6) /** IN endpoint NAK effective */
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#define USB_DIEPINT_emptyintr (1 << 7) /** linux doc broken on this, empty fifo ? */
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#define USB_DIEPINT_txfifoundrn (1 << 8) /** linux doc void on this, tx fifo underrun ? */
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/* the following also apply to DOEPMSK */
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#define USB_DOEPINT_xfercompl (1 << 0) /** Transfer complete */
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#define USB_DOEPINT_epdisabled (1 << 1) /** Endpoint disabled */
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#define USB_DOEPINT_ahberr (1 << 2) /** AHB error */
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#define USB_DOEPINT_setup (1 << 3) /** Setup Phase Done (control EPs)*/
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/* 0<=ep<=15, you can use ep=0 */
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/** Device OUT Endpoint (ep) Control Register */
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#define USB_DOEPCTL(ep) USB_DEV_REG(0x300 + (ep) * 0x20)
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/** Device OUT Endpoint (ep) Frame number Register */
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#define USB_DOEPFN(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x4)
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/** Device Endpoint (ep) Interrupt Register */
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#define USB_DOEPINT(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x8)
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/** Device OUT Endpoint (ep) Transfer Size Register */
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#define USB_DOEPTSIZ(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x10)
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/** Device Endpoint (ep) DMA Address Register */
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#define USB_DOEPDMA(ep) USB_DEV_REG(0x300 + (ep) * 0x20 + 0x14)
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#define USB_PCGCCTL USB_BASE_REG(0xE00) /** Power and Clock Gating Control Register */
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/** Maximum Packet Size
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* IN/OUT EPn
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* IN/OUT EP0 - 2 bits
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* 2'b00: 64 Bytes
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* 2'b01: 32
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* 2'b10: 16
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* 2'b11: 8 */
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#define USB_DEPCTL_mps_bits 0x7ff
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#define USB_DEPCTL_mps_bit_pos 0
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#define USB_DEPCTL_MPS_64 0
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#define USB_DEPCTL_MPS_32 1
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#define USB_DEPCTL_MPS_16 2
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#define USB_DEPCTL_MPS_8 3
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/** Next Endpoint
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* IN EPn/IN EP0
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* OUT EPn/OUT EP0 - reserved */
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#define USB_DEPCTL_nextep_bit_pos 11
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#define USB_DEPCTL_nextep_bits (0xf << USB_DEPCTL_nextep_bit_pos)
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#define USB_DEPCTL_usbactep (1 << 15) /** USB Active Endpoint */
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/** Endpoint DPID (INTR/Bulk IN and OUT endpoints)
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* This field contains the PID of the packet going to
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* be received or transmitted on this endpoint. The
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* application should program the PID of the first
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* packet going to be received or transmitted on this
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* endpoint , after the endpoint is
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* activated. Application use the SetD1PID and
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* SetD0PID fields of this register to program either
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* D0 or D1 PID.
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*
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* The encoding for this field is
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* - 0: D0
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* - 1: D1
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*/
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#define USB_DEPCTL_dpid (1 << 16)
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#define USB_DEPCTL_naksts (1 << 17) /** NAK Status */
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/** Endpoint Type
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* 2'b00: Control
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* 2'b01: Isochronous
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* 2'b10: Bulk
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* 2'b11: Interrupt */
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#define USB_DEPCTL_eptype_bit_pos 18
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#define USB_DEPCTL_eptype_bits (0x3 << USB_DEPCTL_eptype_bit_pos)
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/** Snoop Mode
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* OUT EPn/OUT EP0
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* IN EPn/IN EP0 - reserved */
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#define USB_DEPCTL_snp (1 << 20)
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#define USB_DEPCTL_stall (1 << 21) /** Stall Handshake */
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/** Tx Fifo Number
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* IN EPn/IN EP0
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* OUT EPn/OUT EP0 - reserved */
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#define USB_DEPCTL_txfnum_bit_pos 22
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#define USB_DEPCTL_txfnum_bits (0xf << USB_DEPCTL_txfnum_bit_pos)
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#define USB_DEPCTL_cnak (1 << 26) /** Clear NAK */
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#define USB_DEPCTL_snak (1 << 27) /** Set NAK */
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/** Set DATA0 PID (INTR/Bulk IN and OUT endpoints)
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* Writing to this field sets the Endpoint DPID (DPID)
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* field in this register to DATA0. Set Even
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* (micro)frame (SetEvenFr) (ISO IN and OUT Endpoints)
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* Writing to this field sets the Even/Odd
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* (micro)frame (EO_FrNum) field to even (micro)
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* frame.
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*/
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#define USB_DEPCTL_setd0pid (1 << 28)
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/** Set DATA1 PID (INTR/Bulk IN and OUT endpoints)
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* Writing to this field sets the Endpoint DPID (DPID)
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* field in this register to DATA1 Set Odd
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* (micro)frame (SetOddFr) (ISO IN and OUT Endpoints)
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* Writing to this field sets the Even/Odd
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* (micro)frame (EO_FrNum) field to odd (micro) frame.
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*/
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#define USB_DEPCTL_setd1pid (1 << 29)
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#define USB_DEPCTL_epdis (1 << 30) /** Endpoint disable */
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#define USB_DEPCTL_epena (1 << 31) /** Endpoint enable */
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/* valid for any D{I,O}EPTSIZi with 1<=i<=15, NOT for i=0 ! */
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#define USB_DEPTSIZ_xfersize_bits 0x7ffff /** Transfer Size */
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#define USB_DEPTSIZ_pkcnt_bit_pos 19 /** Packet Count */
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#define USB_DEPTSIZ_pkcnt_bits (0x3ff << USB_DEPTSIZ_pkcnt_bit_pos)
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#define USB_DEPTSIZ_mc_bit_pos 29 /** Multi Count - Periodic IN endpoints */
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#define USB_DEPTSIZ_mc_bits (0x3 << USB_DEPTSIZ_mc_bit_pos)
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/* idem but for i=0 */
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#define USB_DEPTSIZ0_xfersize_bits 0x7f /** Transfer Size */
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#define USB_DEPTSIZ0_pkcnt_bit_pos 19 /** Packet Count */
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#define USB_DEPTSIZ0_pkcnt_bits (0x1 << USB_DEPTSIZ0_pkcnt_bit_pos)
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#define USB_DEPTSIZ0_supcnt_bit_pos 29 /** Setup Packet Count (DOEPTSIZ0 Only) */
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#define USB_DEPTSIZ0_supcnt_bits (0x3 << USB_DEPTSIZ0_supcnt_bit_pos)
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/* valid for USB_DAINT and USB_DAINTMSK, for 0<=ep<=15 */
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#define USB_DAINT_IN_EP(i) (1 << (i))
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#define USB_DAINT_OUT_EP(i) (1 << ((i) + 16))
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/**
|
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* Parameters
|
|
*/
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#define USB_USE_CUSTOM_FIFO_LAYOUT
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#ifdef USB_USE_CUSTOM_FIFO_LAYOUT
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/* Data fifo: includes RX fifo, non period TX fifo and periodic fifos
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* NOTE: this is a hardware parameter, it cannot be changed ! */
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#define USB_DATA_FIFO_DEPTH 0x535
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/* size of the FX fifo */
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#define USB_RX_FIFO_SIZE 0x100
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/* size of the non periodic TX fifo */
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#define USB_NPTX_FIFO_SIZE 0x100
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/* size of each TX ep fifo size */
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#define USB_EPTX_FIFO_SIZE 0x100
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#endif /* USB_USE_CUSTOM_FIFO_LAYOUT */
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|
|
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/* Number of IN/OUT endpoints */
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#define USB_NUM_IN_EP 3
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#define USB_NUM_OUT_EP 2
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|
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/* List of IN enpoints */
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#define USB_IN_EP_LIST 1, 3, 5
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#define USB_OUT_EP_LIST 2, 4
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#endif /* __USB_DRV_AS3525v2_H__ */
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