2011-09-13 23:40:09 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2011 by Amaury Pouly
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "system.h"
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#include "system-target.h"
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#include "lradc-imx233.h"
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2012-01-15 00:38:41 +00:00
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#include "kernel-imx233.h"
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2012-05-19 11:36:23 +00:00
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#include "stdlib.h"
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2011-11-14 21:05:10 +00:00
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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#include "regs/lradc.h"
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/** additional defines */
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#define BP_LRADC_CTRL4_LRADCxSELECT(x) (4 * (x))
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#define BM_LRADC_CTRL4_LRADCxSELECT(x) (0xf << (4 * (x)))
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#define BF_LRADC_CTRL4_LRADCxSELECT(x, v) (((v) << BP_LRADC_CTRL4_LRADCxSELECT(x)) & BM_LRADC_CTRL4_LRADCxSELECT(x))
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#define BFM_LRADC_CTRL4_LRADCxSELECT(x, v) BM_LRADC_CTRL4_LRADCxSELECT(x)
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#define BP_LRADC_CTRL1_LRADCx_IRQ(x) (x)
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#define BM_LRADC_CTRL1_LRADCx_IRQ(x) (1 << (x))
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#define BP_LRADC_CTRL1_LRADCx_IRQ_EN(x) (16 + (x))
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#define BM_LRADC_CTRL1_LRADCx_IRQ_EN(x) (1 << (16 + (x)))
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2011-11-14 21:05:10 +00:00
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/* channels */
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2013-06-16 18:59:36 +00:00
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#if IMX233_SUBTARGET >= 3700
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2012-01-15 00:38:41 +00:00
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static struct channel_arbiter_t channel_arbiter;
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2013-06-16 18:59:36 +00:00
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#else
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static struct semaphore channel_sema[LRADC_NUM_CHANNELS];
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#endif
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2011-11-14 21:05:10 +00:00
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/* delay channels */
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2012-01-15 00:38:41 +00:00
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static struct channel_arbiter_t delay_arbiter;
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2012-03-17 16:39:27 +00:00
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/* battery is very special, dedicate a channel and a delay to it */
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static int battery_chan;
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static int battery_delay_chan;
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2012-05-19 11:36:23 +00:00
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/* irq callbacks */
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2013-06-16 14:43:05 +00:00
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static lradc_irq_fn_t irq_cb[LRADC_NUM_CHANNELS];
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2012-05-19 11:36:23 +00:00
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#define define_cb(x) \
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void INT_LRADC_CH##x(void) \
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{ \
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INT_LRADC_CH(x); \
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}
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void INT_LRADC_CH(int chan)
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{
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if(irq_cb[chan])
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irq_cb[chan](chan);
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2013-06-16 18:59:36 +00:00
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imx233_lradc_clear_channel_irq(chan);
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2012-05-19 11:36:23 +00:00
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}
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define_cb(0)
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define_cb(1)
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define_cb(2)
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define_cb(3)
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define_cb(4)
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define_cb(5)
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define_cb(6)
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define_cb(7)
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void imx233_lradc_set_channel_irq_callback(int channel, lradc_irq_fn_t cb)
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{
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irq_cb[channel] = cb;
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2013-06-16 18:59:36 +00:00
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imx233_icoll_enable_interrupt(INT_SRC_LRADC_CHx(channel), cb != NULL);
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2012-05-19 11:36:23 +00:00
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}
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2011-09-13 23:40:09 +00:00
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2014-02-19 11:56:22 +00:00
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void imx233_lradc_setup_source(int channel, bool div2, int src)
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2011-09-13 23:40:09 +00:00
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{
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if(div2)
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_WR(LRADC_CTRL2_SET, DIVIDE_BY_TWO(1 << channel));
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2011-09-13 23:40:09 +00:00
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else
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_WR(LRADC_CTRL2_CLR, DIVIDE_BY_TWO(1 << channel));
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2013-06-16 18:59:36 +00:00
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#if IMX233_SUBTARGET >= 3700
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_CS(LRADC_CTRL4, LRADCxSELECT(channel, src));
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2013-06-16 18:59:36 +00:00
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#else
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if(channel == 6)
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_CS(LRADC_CTRL2, LRADC6SELECT(src));
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2013-06-16 18:59:36 +00:00
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else if(channel == 7)
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_CS(LRADC_CTRL2, LRADC7SELECT(src));
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2013-06-16 18:59:36 +00:00
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else if(channel != src)
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panicf("cannot configure channel %d for source %d", channel, src);
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#endif
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2011-09-13 23:40:09 +00:00
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}
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2014-02-19 11:56:22 +00:00
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void imx233_lradc_setup_sampling(int channel, bool acc, int nr_samples)
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{
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_CS(LRADC_CHn(channel), NUM_SAMPLES(nr_samples), ACCUMULATE(acc));
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2014-02-19 11:56:22 +00:00
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}
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2011-09-13 23:40:09 +00:00
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void imx233_lradc_setup_delay(int dchan, int trigger_lradc, int trigger_delays,
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int loop_count, int delay)
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{
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_WR_ALL(LRADC_DELAYn(dchan), TRIGGER_LRADCS(trigger_lradc),
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2013-06-16 14:43:05 +00:00
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TRIGGER_DELAYS(trigger_delays), LOOP_COUNT(loop_count), DELAY(delay));
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2011-09-13 23:40:09 +00:00
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}
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2012-05-19 11:36:23 +00:00
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void imx233_lradc_clear_channel_irq(int channel)
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2011-09-13 23:40:09 +00:00
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{
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2013-06-16 14:43:05 +00:00
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BF_CLR(LRADC_CTRL1, LRADCx_IRQ(channel));
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2012-05-19 11:36:23 +00:00
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}
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bool imx233_lradc_read_channel_irq(int channel)
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{
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2013-06-16 14:43:05 +00:00
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return BF_RD(LRADC_CTRL1, LRADCx_IRQ(channel));
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2012-05-19 11:36:23 +00:00
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}
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void imx233_lradc_enable_channel_irq(int channel, bool enable)
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{
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if(enable)
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2013-06-16 14:43:05 +00:00
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BF_SET(LRADC_CTRL1, LRADCx_IRQ_EN(channel));
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2012-05-19 11:36:23 +00:00
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else
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2013-06-16 14:43:05 +00:00
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BF_CLR(LRADC_CTRL1, LRADCx_IRQ_EN(channel));
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2012-05-19 11:36:23 +00:00
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imx233_lradc_clear_channel_irq(channel);
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}
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void imx233_lradc_kick_channel(int channel)
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{
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imx233_lradc_clear_channel_irq(channel);
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_WR(LRADC_CTRL0_SET, SCHEDULE(1 << channel));
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2011-09-13 23:40:09 +00:00
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}
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void imx233_lradc_kick_delay(int dchan)
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{
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_SET(LRADC_DELAYn(dchan), KICK);
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2011-09-13 23:40:09 +00:00
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}
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|
|
void imx233_lradc_wait_channel(int channel)
|
|
|
|
{
|
|
|
|
/* wait for completion */
|
2012-05-19 11:36:23 +00:00
|
|
|
while(!imx233_lradc_read_channel_irq(channel))
|
2011-09-13 23:40:09 +00:00
|
|
|
yield();
|
|
|
|
}
|
|
|
|
|
|
|
|
int imx233_lradc_read_channel(int channel)
|
|
|
|
{
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
return BF_RD(LRADC_CHn(channel), VALUE);
|
2011-09-13 23:40:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_clear_channel(int channel)
|
|
|
|
{
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
BF_CLR(LRADC_CHn(channel), VALUE);
|
2011-09-13 23:40:09 +00:00
|
|
|
}
|
|
|
|
|
2013-06-16 18:59:36 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
|
|
|
int imx233_lradc_acquire_channel(int src, int timeout)
|
2011-09-13 23:40:09 +00:00
|
|
|
{
|
2013-06-16 18:59:36 +00:00
|
|
|
(void) src;
|
2011-11-14 21:05:10 +00:00
|
|
|
return arbiter_acquire(&channel_arbiter, timeout);
|
2011-09-13 23:40:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_release_channel(int chan)
|
|
|
|
{
|
2011-11-14 21:05:10 +00:00
|
|
|
return arbiter_release(&channel_arbiter, chan);
|
2011-09-13 23:40:09 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_reserve_channel(int channel)
|
|
|
|
{
|
2011-11-14 21:05:10 +00:00
|
|
|
return arbiter_reserve(&channel_arbiter, channel);
|
|
|
|
}
|
2013-06-16 18:59:36 +00:00
|
|
|
#else
|
|
|
|
int imx233_lradc_acquire_channel(int src, int timeout)
|
|
|
|
{
|
|
|
|
int channel = src <= LRADC_SRC_BATTERY ? src : 6;
|
|
|
|
if(semaphore_wait(&channel_sema[channel], timeout) == OBJ_WAIT_TIMEDOUT)
|
|
|
|
return -1;
|
|
|
|
return channel;
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_release_channel(int chan)
|
|
|
|
{
|
|
|
|
semaphore_release(&channel_sema[chan]);
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_reserve_channel(int channel)
|
|
|
|
{
|
|
|
|
if(imx233_lradc_acquire_channel(channel, 0) == -1)
|
|
|
|
panicf("Cannot reserve a used channel");
|
|
|
|
}
|
|
|
|
#endif
|
2011-11-14 21:05:10 +00:00
|
|
|
|
|
|
|
int imx233_lradc_acquire_delay(int timeout)
|
|
|
|
{
|
|
|
|
return arbiter_acquire(&delay_arbiter, timeout);
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_release_delay(int chan)
|
|
|
|
{
|
|
|
|
return arbiter_release(&delay_arbiter, chan);
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_reserve_delay(int channel)
|
|
|
|
{
|
|
|
|
return arbiter_reserve(&delay_arbiter, channel);
|
2011-09-13 23:40:09 +00:00
|
|
|
}
|
|
|
|
|
2013-06-16 18:59:36 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2011-09-13 23:40:09 +00:00
|
|
|
int imx233_lradc_sense_die_temperature(int nmos_chan, int pmos_chan)
|
|
|
|
{
|
2014-02-19 11:56:22 +00:00
|
|
|
imx233_lradc_setup_source(nmos_chan, false, LRADC_SRC_NMOS_THIN);
|
|
|
|
imx233_lradc_setup_sampling(nmos_chan, false, 0);
|
|
|
|
imx233_lradc_setup_source(pmos_chan, false, LRADC_SRC_PMOS_THIN);
|
|
|
|
imx233_lradc_setup_sampling(pmos_chan, false, 0);
|
2011-09-13 23:40:09 +00:00
|
|
|
// mux sensors
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_CLR(LRADC_CTRL2, TEMPSENSE_PWD);
|
2011-09-13 23:40:09 +00:00
|
|
|
imx233_lradc_clear_channel(nmos_chan);
|
|
|
|
imx233_lradc_clear_channel(pmos_chan);
|
|
|
|
// schedule both channels
|
|
|
|
imx233_lradc_kick_channel(nmos_chan);
|
|
|
|
imx233_lradc_kick_channel(pmos_chan);
|
|
|
|
// wait completion
|
|
|
|
imx233_lradc_wait_channel(nmos_chan);
|
|
|
|
imx233_lradc_wait_channel(pmos_chan);
|
|
|
|
// mux sensors
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_SET(LRADC_CTRL2, TEMPSENSE_PWD);
|
2011-09-13 23:40:09 +00:00
|
|
|
// do the computation
|
|
|
|
int diff = imx233_lradc_read_channel(nmos_chan) - imx233_lradc_read_channel(pmos_chan);
|
|
|
|
// return diff * 1.012 / 4
|
|
|
|
return (diff * 1012) / 4000;
|
|
|
|
}
|
2013-06-16 18:59:36 +00:00
|
|
|
#endif
|
2011-09-13 23:40:09 +00:00
|
|
|
|
2012-03-17 16:39:27 +00:00
|
|
|
/* set to 0 to disable current source */
|
|
|
|
static void imx233_lradc_set_temp_isrc(int sensor, int value)
|
|
|
|
{
|
|
|
|
if(sensor < 0 || sensor > 1)
|
|
|
|
panicf("imx233_lradc_set_temp_isrc: invalid sensor");
|
2013-06-16 14:43:05 +00:00
|
|
|
unsigned mask = sensor ? BM_LRADC_CTRL2_TEMP_ISRC0 : BM_LRADC_CTRL2_TEMP_ISRC1;
|
|
|
|
unsigned bp = sensor ? BP_LRADC_CTRL2_TEMP_ISRC0 : BP_LRADC_CTRL2_TEMP_ISRC1;
|
|
|
|
unsigned en = sensor ? BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE0 : BM_LRADC_CTRL2_TEMP_SENSOR_IENABLE1;
|
2012-03-17 16:39:27 +00:00
|
|
|
|
2013-06-16 14:43:05 +00:00
|
|
|
HW_LRADC_CTRL2_CLR = mask;
|
|
|
|
HW_LRADC_CTRL2_SET = value << bp;
|
2012-03-17 16:39:27 +00:00
|
|
|
if(value != 0)
|
|
|
|
{
|
2013-06-16 14:43:05 +00:00
|
|
|
HW_LRADC_CTRL2_SET = en;
|
2012-03-17 16:39:27 +00:00
|
|
|
udelay(100);
|
|
|
|
}
|
|
|
|
else
|
2013-06-16 14:43:05 +00:00
|
|
|
HW_LRADC_CTRL2_CLR = en;
|
2012-03-17 16:39:27 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int imx233_lradc_sense_ext_temperature(int chan, int sensor)
|
|
|
|
{
|
|
|
|
#define EXT_TEMP_ACC_COUNT 5
|
|
|
|
/* setup channel */
|
2014-02-19 11:56:22 +00:00
|
|
|
imx233_lradc_setup_source(chan, false, sensor);
|
|
|
|
imx233_lradc_setup_sampling(chan, false, 0);
|
2012-03-17 16:39:27 +00:00
|
|
|
/* set current source to 300µA */
|
2013-06-16 14:43:05 +00:00
|
|
|
imx233_lradc_set_temp_isrc(sensor, BV_LRADC_CTRL2_TEMP_ISRC0__300);
|
2012-03-17 16:39:27 +00:00
|
|
|
/* read value and accumulate */
|
|
|
|
int a = 0;
|
|
|
|
for(int i = 0; i < EXT_TEMP_ACC_COUNT; i++)
|
|
|
|
{
|
|
|
|
imx233_lradc_clear_channel(chan);
|
|
|
|
imx233_lradc_kick_channel(chan);
|
|
|
|
imx233_lradc_wait_channel(chan);
|
|
|
|
a += imx233_lradc_read_channel(chan);
|
|
|
|
}
|
|
|
|
/* setup channel for small accumulation */
|
|
|
|
/* set current source to 20µA */
|
2013-06-16 14:43:05 +00:00
|
|
|
imx233_lradc_set_temp_isrc(sensor, BV_LRADC_CTRL2_TEMP_ISRC0__20);
|
2012-03-17 16:39:27 +00:00
|
|
|
/* read value */
|
|
|
|
int b = 0;
|
|
|
|
for(int i = 0; i < EXT_TEMP_ACC_COUNT; i++)
|
|
|
|
{
|
|
|
|
imx233_lradc_clear_channel(chan);
|
|
|
|
imx233_lradc_kick_channel(chan);
|
|
|
|
imx233_lradc_wait_channel(chan);
|
|
|
|
b += imx233_lradc_read_channel(chan);
|
|
|
|
}
|
|
|
|
/* disable sensor current */
|
2013-06-16 14:43:05 +00:00
|
|
|
imx233_lradc_set_temp_isrc(sensor, BV_LRADC_CTRL2_TEMP_ISRC0__ZERO);
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
|
2012-05-19 11:36:23 +00:00
|
|
|
return (abs(b - a) / EXT_TEMP_ACC_COUNT) * 1104 / 1000;
|
2012-03-17 16:39:27 +00:00
|
|
|
}
|
|
|
|
|
2011-11-14 21:47:59 +00:00
|
|
|
void imx233_lradc_setup_battery_conversion(bool automatic, unsigned long scale_factor)
|
2011-11-14 21:05:10 +00:00
|
|
|
{
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
BF_CS(LRADC_CONVERSION, SCALE_FACTOR(scale_factor));
|
2011-11-14 21:47:59 +00:00
|
|
|
if(automatic)
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_SET(LRADC_CONVERSION, AUTOMATIC);
|
2011-11-14 21:47:59 +00:00
|
|
|
else
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_CLR(LRADC_CONVERSION, AUTOMATIC);
|
2011-11-14 21:05:10 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
int imx233_lradc_read_battery_voltage(void)
|
|
|
|
{
|
2013-06-16 14:43:05 +00:00
|
|
|
return BF_RD(LRADC_CONVERSION, SCALED_BATT_VOLTAGE);
|
2011-11-14 21:05:10 +00:00
|
|
|
}
|
|
|
|
|
2012-05-19 11:36:23 +00:00
|
|
|
void imx233_lradc_setup_touch(bool xminus_enable, bool yminus_enable,
|
|
|
|
bool xplus_enable, bool yplus_enable, bool touch_detect)
|
|
|
|
{
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
BF_CS(LRADC_CTRL0, XMINUS_ENABLE(xminus_enable),
|
2013-06-16 14:43:05 +00:00
|
|
|
YMINUS_ENABLE(yminus_enable), XPLUS_ENABLE(xplus_enable),
|
|
|
|
YPLUS_ENABLE(yplus_enable), TOUCH_DETECT_ENABLE(touch_detect));
|
2012-05-19 11:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_enable_touch_detect_irq(bool enable)
|
|
|
|
{
|
2013-06-16 14:43:05 +00:00
|
|
|
if(enable)
|
|
|
|
BF_SET(LRADC_CTRL1, TOUCH_DETECT_IRQ_EN);
|
|
|
|
else
|
|
|
|
BF_CLR(LRADC_CTRL1, TOUCH_DETECT_IRQ_EN);
|
2012-05-19 11:36:23 +00:00
|
|
|
imx233_lradc_clear_touch_detect_irq();
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_lradc_clear_touch_detect_irq(void)
|
|
|
|
{
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_CLR(LRADC_CTRL1, TOUCH_DETECT_IRQ);
|
2012-05-19 11:36:23 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool imx233_lradc_read_touch_detect(void)
|
|
|
|
{
|
2013-06-16 14:43:05 +00:00
|
|
|
return BF_RD(LRADC_STATUS, TOUCH_DETECT_RAW);
|
2012-05-19 11:36:23 +00:00
|
|
|
}
|
|
|
|
|
2011-09-13 23:40:09 +00:00
|
|
|
void imx233_lradc_init(void)
|
|
|
|
{
|
2013-06-16 18:59:36 +00:00
|
|
|
/* On STMP3700+, any channel can measure any source but on STMP3600 only
|
|
|
|
* channels 6 and 7 can measure all sources. Channel 7 being dedicated to
|
|
|
|
* battery, only channel 6 is available for free use */
|
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2013-06-16 14:43:05 +00:00
|
|
|
arbiter_init(&channel_arbiter, LRADC_NUM_CHANNELS);
|
2013-06-16 18:59:36 +00:00
|
|
|
#else
|
|
|
|
for(int i = 0; i < LRADC_NUM_CHANNELS; i++)
|
|
|
|
semaphore_init(&channel_sema[i], 1, 1);
|
|
|
|
#endif
|
2013-06-16 14:43:05 +00:00
|
|
|
arbiter_init(&delay_arbiter, LRADC_NUM_DELAYS);
|
2011-09-13 23:40:09 +00:00
|
|
|
// enable block
|
|
|
|
imx233_reset_block(&HW_LRADC_CTRL0);
|
|
|
|
// disable ground ref
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_CLR(LRADC_CTRL0, ONCHIP_GROUNDREF);
|
2011-09-13 23:40:09 +00:00
|
|
|
// disable temperature sensors
|
2013-06-16 14:43:05 +00:00
|
|
|
BF_CLR(LRADC_CTRL2, TEMP_SENSOR_IENABLE0);
|
|
|
|
BF_CLR(LRADC_CTRL2, TEMP_SENSOR_IENABLE1);
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2013-06-16 18:59:36 +00:00
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#if IMX233_SUBTARGET >= 3700
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2013-06-16 14:43:05 +00:00
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BF_SET(LRADC_CTRL2, TEMPSENSE_PWD);
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2013-06-16 18:59:36 +00:00
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#endif
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2011-09-13 23:40:09 +00:00
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// set frequency
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imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
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BF_CS(LRADC_CTRL3, CYCLE_TIME_V(6MHZ));
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2012-03-17 16:39:27 +00:00
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// setup battery
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battery_chan = 7;
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imx233_lradc_reserve_channel(battery_chan);
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/* setup them for the simplest use: no accumulation, no division*/
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2014-02-19 11:56:22 +00:00
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imx233_lradc_setup_source(battery_chan, false, LRADC_SRC_BATTERY);
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imx233_lradc_setup_sampling(battery_chan, false, 0);
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2012-03-17 16:39:27 +00:00
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/* setup delay channel for battery for automatic reading and scaling */
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battery_delay_chan = 0;
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imx233_lradc_reserve_delay(battery_delay_chan);
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/* setup delay to trigger battery channel and retrigger itself.
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* The counter runs at 2KHz so a delay of 200 will trigger 10
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* conversions per seconds */
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imx233_lradc_setup_delay(battery_delay_chan, 1 << battery_chan,
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1 << battery_delay_chan, 0, 200);
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imx233_lradc_kick_delay(battery_delay_chan);
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/* enable automatic conversion, use Li-Ion type battery */
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2013-06-16 14:43:05 +00:00
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imx233_lradc_setup_battery_conversion(true, BV_LRADC_CONVERSION_SCALE_FACTOR__LI_ION);
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2011-09-13 23:40:09 +00:00
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}
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