2011-05-01 13:02:46 +00:00
|
|
|
/***************************************************************************
|
|
|
|
* __________ __ ___.
|
|
|
|
* Open \______ \ ____ ____ | | _\_ |__ _______ ___
|
|
|
|
* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
|
|
|
|
* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
|
|
|
|
* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
|
|
|
|
* \/ \/ \/ \/ \/
|
|
|
|
* $Id$
|
|
|
|
*
|
2012-12-29 00:32:59 +00:00
|
|
|
* Copyright (C) 2011 by Amaury Pouly
|
2011-05-01 13:02:46 +00:00
|
|
|
*
|
|
|
|
* This program is free software; you can redistribute it and/or
|
|
|
|
* modify it under the terms of the GNU General Public License
|
|
|
|
* as published by the Free Software Foundation; either version 2
|
|
|
|
* of the License, or (at your option) any later version.
|
|
|
|
*
|
|
|
|
* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
|
|
|
|
* KIND, either express or implied.
|
|
|
|
*
|
|
|
|
****************************************************************************/
|
|
|
|
|
|
|
|
#include "kernel.h"
|
|
|
|
#include "system.h"
|
|
|
|
#include "gcc_extensions.h"
|
|
|
|
#include "system-target.h"
|
|
|
|
#include "cpu.h"
|
|
|
|
#include "clkctrl-imx233.h"
|
|
|
|
#include "pinctrl-imx233.h"
|
|
|
|
#include "timrot-imx233.h"
|
2011-06-17 22:30:58 +00:00
|
|
|
#include "dma-imx233.h"
|
|
|
|
#include "ssp-imx233.h"
|
2011-07-03 15:18:41 +00:00
|
|
|
#include "i2c-imx233.h"
|
2013-06-16 22:28:19 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2012-01-15 00:38:41 +00:00
|
|
|
#include "dcp-imx233.h"
|
2013-06-16 22:28:19 +00:00
|
|
|
#endif
|
2012-05-19 11:40:34 +00:00
|
|
|
#include "pwm-imx233.h"
|
2012-05-19 11:23:17 +00:00
|
|
|
#include "icoll-imx233.h"
|
2012-03-17 16:39:27 +00:00
|
|
|
#include "lradc-imx233.h"
|
2012-05-19 10:57:04 +00:00
|
|
|
#include "rtc-imx233.h"
|
2012-08-30 18:56:39 +00:00
|
|
|
#include "power-imx233.h"
|
2013-01-10 00:43:08 +00:00
|
|
|
#include "emi-imx233.h"
|
2011-05-01 13:02:46 +00:00
|
|
|
#include "lcd.h"
|
|
|
|
#include "backlight-target.h"
|
2012-01-08 00:18:43 +00:00
|
|
|
#include "button.h"
|
2012-03-15 13:59:20 +00:00
|
|
|
#include "fmradio_i2c.h"
|
2013-11-19 22:12:42 +00:00
|
|
|
#include "powermgmt-imx233.h"
|
2017-01-11 15:58:30 +00:00
|
|
|
#include "led-imx233.h"
|
2011-05-01 13:02:46 +00:00
|
|
|
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
#include "regs/digctl.h"
|
|
|
|
#include "regs/usbphy.h"
|
|
|
|
#include "regs/timrot.h"
|
|
|
|
|
2014-02-02 03:31:54 +00:00
|
|
|
#define WATCHDOG_HW_DELAY (10 * HZ)
|
|
|
|
#define WATCHDOG_SW_DELAY (5 * HZ)
|
|
|
|
|
2017-10-13 04:28:50 +00:00
|
|
|
static struct mutex cpufreq_mtx;
|
|
|
|
|
2016-09-20 23:09:23 +00:00
|
|
|
void UIE(unsigned int pc, unsigned int num);
|
|
|
|
|
2014-02-02 03:31:54 +00:00
|
|
|
static void woof_woof(void)
|
|
|
|
{
|
2016-09-20 23:09:23 +00:00
|
|
|
/* stop hardware watchdog, we catched the error */
|
2014-02-02 03:31:54 +00:00
|
|
|
imx233_rtc_enable_watchdog(false);
|
2016-09-20 23:09:23 +00:00
|
|
|
/* recover current PC and trigger abort, so in the hope to get a useful
|
|
|
|
* backtrace */
|
2014-02-02 03:31:54 +00:00
|
|
|
uint32_t pc = HW_DIGCTL_SCRATCH0;
|
2016-09-20 23:09:23 +00:00
|
|
|
UIE(pc, 4);
|
2014-02-02 03:31:54 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static void good_dog(void)
|
|
|
|
{
|
|
|
|
imx233_rtc_reset_watchdog(WATCHDOG_HW_DELAY * 1000 / HZ); /* ms */
|
|
|
|
imx233_rtc_enable_watchdog(true);
|
2016-05-02 20:37:38 +00:00
|
|
|
imx233_timrot_setup_simple(TIMER_WATCHDOG, false, WATCHDOG_SW_DELAY * 1000 / HZ,
|
|
|
|
TIMER_SRC_1KHZ, &woof_woof);
|
2014-02-02 03:31:54 +00:00
|
|
|
imx233_timrot_set_priority(TIMER_WATCHDOG, ICOLL_PRIO_WATCHDOG);
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_keep_alive(void)
|
|
|
|
{
|
|
|
|
/* setting up a timer is not exactly a cheap operation so only do so
|
|
|
|
* every second */
|
|
|
|
static uint32_t last_alive = 0;
|
|
|
|
if(imx233_us_elapsed(last_alive, 1000000))
|
|
|
|
{
|
|
|
|
good_dog();
|
|
|
|
last_alive = HW_DIGCTL_MICROSECONDS;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void watchdog_init(void)
|
|
|
|
{
|
|
|
|
/* setup two mechanisms:
|
|
|
|
* - hardware watchdog to reset the player after 10 seconds
|
|
|
|
* - software watchdog using a timer to panic after 5 seconds
|
|
|
|
* The hardware mechanism ensures reset when the player is completely
|
|
|
|
* dead and it actually resets the whole chip. On the contrary, the software
|
|
|
|
* mechanism allows partial recovery by panicing and printing (maybe) useful
|
|
|
|
* information, it uses a dedicated timer with the highest level of interrupt
|
|
|
|
* priority so it works even if the player is stuck in IRQ context */
|
|
|
|
good_dog();
|
|
|
|
}
|
|
|
|
|
2016-09-26 20:24:00 +00:00
|
|
|
void imx233_system_prepare_shutdown(void)
|
|
|
|
{
|
|
|
|
/* wait a bit, useful for the user to stop touching anything */
|
|
|
|
sleep(HZ / 2);
|
|
|
|
/* disable watchdog just in case since we will disable interrupts */
|
|
|
|
imx233_rtc_enable_watchdog(false);
|
|
|
|
/* disable interrupts, it's probably better to avoid any action so close
|
|
|
|
* to shutdown */
|
|
|
|
disable_interrupt(IRQ_FIQ_STATUS);
|
|
|
|
#ifdef SANSA_FUZEPLUS
|
|
|
|
/* This pin seems to be important to shutdown the hardware properly */
|
|
|
|
imx233_pinctrl_acquire(0, 9, "power off");
|
|
|
|
imx233_pinctrl_set_function(0, 9, PINCTRL_FUNCTION_GPIO);
|
|
|
|
imx233_pinctrl_enable_gpio(0, 9, true);
|
|
|
|
imx233_pinctrl_set_gpio(0, 9, true);
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
2011-09-13 23:38:49 +00:00
|
|
|
void imx233_chip_reset(void)
|
2011-05-01 13:02:46 +00:00
|
|
|
{
|
2013-06-16 22:28:19 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2013-06-16 13:28:04 +00:00
|
|
|
HW_CLKCTRL_RESET = BM_CLKCTRL_RESET_CHIP;
|
2013-06-16 22:28:19 +00:00
|
|
|
#else
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
BF_WR_ALL(POWER_RESET, UNLOCK_V(KEY), RST_DIG(1));
|
2013-06-16 22:28:19 +00:00
|
|
|
#endif
|
2011-05-01 13:02:46 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void system_reboot(void)
|
|
|
|
{
|
2016-09-26 20:24:00 +00:00
|
|
|
imx233_system_prepare_shutdown();
|
|
|
|
/* reset */
|
2011-05-01 13:02:46 +00:00
|
|
|
imx233_chip_reset();
|
|
|
|
while(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
void system_exception_wait(void)
|
|
|
|
{
|
2014-02-18 17:20:57 +00:00
|
|
|
/* stop hadrware watchdog, IRQs are stopped */
|
|
|
|
imx233_rtc_enable_watchdog(false);
|
2011-06-30 17:31:40 +00:00
|
|
|
/* make sure lcd and backlight are on */
|
2011-11-17 23:10:22 +00:00
|
|
|
lcd_update();
|
2015-01-08 23:22:40 +00:00
|
|
|
backlight_hw_on();
|
|
|
|
backlight_hw_brightness(DEFAULT_BRIGHTNESS_SETTING);
|
2016-05-02 20:41:02 +00:00
|
|
|
/* wait until button release (if a button is pressed)
|
|
|
|
* NOTE at this point, interrupts are off so that rules out touchpad and
|
|
|
|
* ADC, so we are pretty much left with PSWITCH only. If other buttons are
|
|
|
|
* wanted, it is possible to implement a busy polling version of button
|
|
|
|
* reading for GPIO and ADC in button-imx233 but this is not done at the
|
|
|
|
* moment. */
|
|
|
|
while(imx233_power_read_pswitch() != 0) {}
|
|
|
|
while(imx233_power_read_pswitch() == 0) {}
|
|
|
|
while(imx233_power_read_pswitch() != 0) {}
|
2011-05-01 13:02:46 +00:00
|
|
|
}
|
|
|
|
|
2011-09-06 00:27:38 +00:00
|
|
|
int system_memory_guard(int newmode)
|
|
|
|
{
|
|
|
|
(void)newmode;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-07-23 11:45:18 +00:00
|
|
|
static void set_page_tables(void)
|
|
|
|
{
|
|
|
|
/* map every memory region to itself */
|
|
|
|
map_section(0, 0, 0x1000, CACHE_NONE);
|
|
|
|
|
|
|
|
/* map RAM and enable caching for it */
|
2011-09-05 11:29:32 +00:00
|
|
|
map_section(DRAM_ORIG, CACHED_DRAM_ADDR, MEMORYSIZE, CACHE_ALL);
|
|
|
|
map_section(DRAM_ORIG, BUFFERED_DRAM_ADDR, MEMORYSIZE, BUFFERED);
|
2011-07-23 11:45:18 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void memory_init(void)
|
|
|
|
{
|
|
|
|
ttb_init();
|
|
|
|
set_page_tables();
|
|
|
|
enable_mmu();
|
|
|
|
}
|
|
|
|
|
2011-05-01 13:02:46 +00:00
|
|
|
void system_init(void)
|
|
|
|
{
|
2012-12-29 00:33:55 +00:00
|
|
|
/* NOTE: don't use anything here that might require tick task !
|
|
|
|
* It is initialized by kernel_init *after* system_init().
|
|
|
|
* The main() will naturally set cpu speed to normal after kernel_init()
|
2013-06-16 18:08:49 +00:00
|
|
|
* so don't bother if the cpu is running at 24MHz here.
|
|
|
|
* Make sure IO clock is running at expected speed */
|
2017-10-13 04:28:50 +00:00
|
|
|
mutex_init(&cpufreq_mtx);
|
2013-06-16 18:08:49 +00:00
|
|
|
imx233_clkctrl_init();
|
|
|
|
imx233_clkctrl_enable(CLK_PLL, true);
|
2013-06-16 22:28:19 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2013-06-16 18:08:49 +00:00
|
|
|
imx233_clkctrl_set_frac_div(CLK_IO, 18); // clk_io@clk_pll
|
2013-06-16 22:28:19 +00:00
|
|
|
#endif
|
2013-06-16 18:08:49 +00:00
|
|
|
|
2012-05-19 10:57:04 +00:00
|
|
|
imx233_rtc_init();
|
2012-05-19 11:23:17 +00:00
|
|
|
imx233_icoll_init();
|
2011-05-01 13:02:46 +00:00
|
|
|
imx233_pinctrl_init();
|
|
|
|
imx233_timrot_init();
|
2011-06-17 22:30:58 +00:00
|
|
|
imx233_dma_init();
|
|
|
|
imx233_ssp_init();
|
2013-06-16 22:28:19 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2012-01-15 00:38:41 +00:00
|
|
|
imx233_dcp_init();
|
2013-06-16 22:28:19 +00:00
|
|
|
#endif
|
2012-05-19 11:40:34 +00:00
|
|
|
imx233_pwm_init();
|
2012-03-17 16:39:27 +00:00
|
|
|
imx233_lradc_init();
|
2012-12-29 00:33:55 +00:00
|
|
|
imx233_power_init();
|
2012-03-15 13:59:20 +00:00
|
|
|
imx233_i2c_init();
|
2013-07-07 15:29:41 +00:00
|
|
|
imx233_powermgmt_init();
|
2017-01-11 15:58:30 +00:00
|
|
|
imx233_led_init();
|
2014-02-02 03:31:54 +00:00
|
|
|
/* setup watchdog */
|
|
|
|
watchdog_init();
|
2012-12-29 00:33:55 +00:00
|
|
|
|
2013-06-16 18:08:49 +00:00
|
|
|
/* make sure auto-slow is disable now, we don't know at which frequency we
|
|
|
|
* are running and auto-slow could violate constraints on {xbus,hbus} */
|
|
|
|
imx233_clkctrl_enable_auto_slow(false);
|
|
|
|
imx233_clkctrl_set_auto_slow_div(BV_CLKCTRL_HBUS_SLOW_DIV__BY8);
|
2012-12-29 00:33:55 +00:00
|
|
|
|
2016-05-02 20:39:58 +00:00
|
|
|
cpu_frequency = imx233_clkctrl_get_freq(CLK_CPU) * 1000; /* variable in Hz */
|
2013-01-13 00:55:34 +00:00
|
|
|
|
2013-12-02 19:09:56 +00:00
|
|
|
#if !defined(BOOTLOADER) && CONFIG_TUNER != 0
|
2012-12-29 00:33:55 +00:00
|
|
|
fmradio_i2c_init();
|
|
|
|
#endif
|
2011-05-01 13:02:46 +00:00
|
|
|
}
|
|
|
|
|
2014-02-10 21:28:46 +00:00
|
|
|
void system_prepare_fw_start(void)
|
|
|
|
{
|
|
|
|
/* keep alive to get enough time, stop watchdog */
|
|
|
|
imx233_keep_alive();
|
|
|
|
imx233_rtc_enable_watchdog(false);
|
|
|
|
}
|
|
|
|
|
2011-05-01 13:02:46 +00:00
|
|
|
bool imx233_us_elapsed(uint32_t ref, unsigned us_delay)
|
|
|
|
{
|
|
|
|
uint32_t cur = HW_DIGCTL_MICROSECONDS;
|
|
|
|
if(ref + us_delay <= ref)
|
|
|
|
return !(cur > ref) && !(cur < (ref + us_delay));
|
|
|
|
else
|
|
|
|
return (cur < ref) || cur >= (ref + us_delay);
|
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_reset_block(volatile uint32_t *block_reg)
|
|
|
|
{
|
2013-09-18 11:03:31 +00:00
|
|
|
/* deassert reset and clock gate */
|
|
|
|
__REG_CLR(*block_reg) = __BLOCK_SFTRST;
|
|
|
|
while(*block_reg & __BLOCK_SFTRST);
|
|
|
|
__REG_CLR(*block_reg) = __BLOCK_CLKGATE;
|
|
|
|
while(*block_reg & __BLOCK_CLKGATE);
|
2011-09-13 23:38:49 +00:00
|
|
|
/* soft-reset */
|
2011-05-01 13:02:46 +00:00
|
|
|
__REG_SET(*block_reg) = __BLOCK_SFTRST;
|
2011-09-13 23:38:49 +00:00
|
|
|
/* make sure block is gated off */
|
2011-05-01 13:02:46 +00:00
|
|
|
while(!(*block_reg & __BLOCK_CLKGATE));
|
2011-09-13 23:38:49 +00:00
|
|
|
/* bring block out of reset */
|
2011-05-01 13:02:46 +00:00
|
|
|
__REG_CLR(*block_reg) = __BLOCK_SFTRST;
|
|
|
|
while(*block_reg & __BLOCK_SFTRST);
|
2011-09-13 23:38:49 +00:00
|
|
|
/* make sure clock is running */
|
2011-05-01 13:02:46 +00:00
|
|
|
__REG_CLR(*block_reg) = __BLOCK_CLKGATE;
|
|
|
|
while(*block_reg & __BLOCK_CLKGATE);
|
|
|
|
}
|
|
|
|
|
|
|
|
void udelay(unsigned us)
|
|
|
|
{
|
|
|
|
uint32_t ref = HW_DIGCTL_MICROSECONDS;
|
2017-08-27 13:56:11 +00:00
|
|
|
/* increase number of us by 1 to make sure we wait *at least* the requested
|
|
|
|
* time */
|
|
|
|
while(!imx233_us_elapsed(ref, us + 1));
|
2011-05-01 13:02:46 +00:00
|
|
|
}
|
|
|
|
|
2013-01-10 01:02:12 +00:00
|
|
|
void imx233_digctl_set_arm_cache_timings(unsigned timings)
|
|
|
|
{
|
2013-06-16 22:28:19 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3780
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
BF_WR_ALL(DIGCTL_ARMCACHE, ITAG_SS(timings),
|
2013-06-16 15:56:10 +00:00
|
|
|
DTAG_SS(timings), CACHE_SS(timings), DRTY_SS(timings), VALID_SS(timings));
|
2013-06-16 22:28:19 +00:00
|
|
|
#else
|
imx233: generate register headers using headergen_v2 and update code for it
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
2016-05-24 19:29:56 +00:00
|
|
|
BF_WR_ALL(DIGCTL_ARMCACHE, ITAG_SS(timings),
|
2013-06-16 22:28:19 +00:00
|
|
|
DTAG_SS(timings), CACHE_SS(timings));
|
|
|
|
#endif
|
2013-01-10 01:02:12 +00:00
|
|
|
}
|
|
|
|
|
2013-01-13 00:55:34 +00:00
|
|
|
struct cpufreq_profile_t
|
|
|
|
{
|
|
|
|
/* key */
|
|
|
|
long cpu_freq;
|
|
|
|
/* parameters */
|
|
|
|
int vddd, vddd_bo;
|
|
|
|
int hbus_div;
|
|
|
|
int cpu_idiv, cpu_fdiv;
|
|
|
|
long emi_freq;
|
|
|
|
int arm_cache_timings;
|
|
|
|
};
|
|
|
|
|
2014-06-22 10:56:47 +00:00
|
|
|
/* Some devices don't handle very well memory frequency changes, so avoid them
|
|
|
|
* by running at highest speed at all time */
|
|
|
|
#if defined(CREATIVE_ZEN) || defined(CREATIVE_ZENXFI)
|
2017-08-27 15:24:49 +00:00
|
|
|
#define EMIFREQ_NORMAL IMX233_EMIFREQ_130_MHz
|
|
|
|
#define EMIFREQ_MAX IMX233_EMIFREQ_130_MHz
|
|
|
|
/* we need a VDDD of at least 1.2V to run the EMI at 130Mhz */
|
|
|
|
#define VDDD_MIN 1275
|
2014-06-22 10:56:47 +00:00
|
|
|
#else /* weird targets */
|
|
|
|
#define EMIFREQ_NORMAL IMX233_EMIFREQ_64_MHz
|
|
|
|
#define EMIFREQ_MAX IMX233_EMIFREQ_130_MHz
|
2017-08-27 15:24:49 +00:00
|
|
|
#define VDDD_MIN 1050
|
2014-06-22 10:56:47 +00:00
|
|
|
#endif
|
|
|
|
|
2014-03-08 17:22:47 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2013-01-13 00:55:34 +00:00
|
|
|
static struct cpufreq_profile_t cpu_profiles[] =
|
|
|
|
{
|
2014-03-08 17:22:47 +00:00
|
|
|
/* clk_p@454.74 MHz, clk_h@151.58 MHz, clk_emi@130.91 MHz, VDDD@1.550 V */
|
2014-06-22 10:56:47 +00:00
|
|
|
{IMX233_CPUFREQ_454_MHz, 1550, 1450, 3, 1, 19, EMIFREQ_MAX, 0},
|
2014-03-08 17:22:47 +00:00
|
|
|
/* clk_p@320.00 MHz, clk_h@106.66 MHz, clk_emi@130.91 MHz, VDDD@1.450 V */
|
2014-06-22 10:56:47 +00:00
|
|
|
{IMX233_CPUFREQ_320_MHz, 1450, 1350, 3, 1, 27, EMIFREQ_MAX, 0},
|
2013-07-01 22:31:57 +00:00
|
|
|
/* clk_p@261.82 MHz, clk_h@130.91 MHz, clk_emi@130.91 MHz, VDDD@1.275 V */
|
2014-06-22 10:56:47 +00:00
|
|
|
{IMX233_CPUFREQ_261_MHz, 1275, 1175, 2, 1, 33, EMIFREQ_MAX, 0},
|
2017-08-27 15:24:49 +00:00
|
|
|
/* clk_p@64 MHz, clk_h@64 MHz, clk_emi@64 MHz, VDDD@1.050 V (or 1.275V) */
|
|
|
|
{IMX233_CPUFREQ_64_MHz, VDDD_MIN, 975, 1, 5, 27, EMIFREQ_NORMAL, 3},
|
2013-01-13 00:55:34 +00:00
|
|
|
/* dummy */
|
|
|
|
{0, 0, 0, 0, 0, 0, 0, 0}
|
|
|
|
};
|
2013-10-21 22:16:22 +00:00
|
|
|
#endif
|
2013-01-13 00:55:34 +00:00
|
|
|
|
|
|
|
#define NR_CPU_PROFILES ((int)(sizeof(cpu_profiles)/sizeof(cpu_profiles[0])))
|
|
|
|
|
2013-09-25 12:12:48 +00:00
|
|
|
void imx233_set_cpu_frequency(long frequency)
|
2011-06-30 17:31:40 +00:00
|
|
|
{
|
2014-03-08 17:22:47 +00:00
|
|
|
#if IMX233_SUBTARGET >= 3700
|
2012-12-26 00:12:24 +00:00
|
|
|
/* don't change the frequency if it is useless (changes are expensive) */
|
|
|
|
if(cpu_frequency == frequency)
|
|
|
|
return;
|
2013-01-13 00:55:34 +00:00
|
|
|
|
|
|
|
struct cpufreq_profile_t *prof = cpu_profiles;
|
|
|
|
while(prof->cpu_freq != 0 && prof->cpu_freq != frequency)
|
|
|
|
prof++;
|
|
|
|
if(prof->cpu_freq == 0)
|
|
|
|
return;
|
2012-12-26 00:12:24 +00:00
|
|
|
/* disable auto-slow (enable back afterwards) */
|
|
|
|
imx233_clkctrl_enable_auto_slow(false);
|
|
|
|
|
2013-01-13 00:55:34 +00:00
|
|
|
/* WARNING watch out the order ! */
|
|
|
|
if(frequency > cpu_frequency)
|
2011-06-30 17:31:40 +00:00
|
|
|
{
|
2013-01-13 00:55:34 +00:00
|
|
|
/* Change VDDD regulator */
|
|
|
|
imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
|
|
|
|
/* Change ARM cache timings */
|
|
|
|
imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
|
2014-03-08 17:49:38 +00:00
|
|
|
/* Change CPU and HBUS frequencies */
|
|
|
|
imx233_clkctrl_set_cpu_hbus_div(prof->cpu_idiv, prof->cpu_fdiv, prof->hbus_div);
|
2013-01-13 00:55:34 +00:00
|
|
|
/* Set the new EMI frequency */
|
|
|
|
imx233_emi_set_frequency(prof->emi_freq);
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2014-03-08 17:49:38 +00:00
|
|
|
/* Change CPU and HBUS frequencies */
|
|
|
|
imx233_clkctrl_set_cpu_hbus_div(prof->cpu_idiv, prof->cpu_fdiv, prof->hbus_div);
|
2013-01-13 00:55:34 +00:00
|
|
|
/* Set the new EMI frequency */
|
|
|
|
imx233_emi_set_frequency(prof->emi_freq);
|
|
|
|
/* Change ARM cache timings */
|
|
|
|
imx233_digctl_set_arm_cache_timings(prof->arm_cache_timings);
|
|
|
|
/* Change VDDD regulator */
|
|
|
|
imx233_power_set_regulator(REGULATOR_VDDD, prof->vddd, prof->vddd_bo);
|
2011-06-30 17:31:40 +00:00
|
|
|
}
|
2012-12-26 00:12:24 +00:00
|
|
|
/* enable auto slow again */
|
2013-06-16 18:08:49 +00:00
|
|
|
imx233_clkctrl_enable_auto_slow(true);
|
2013-01-13 00:55:34 +00:00
|
|
|
/* update frequency */
|
|
|
|
cpu_frequency = frequency;
|
2013-10-21 22:16:22 +00:00
|
|
|
#else
|
|
|
|
(void) frequency;
|
|
|
|
#endif
|
2011-06-30 17:31:40 +00:00
|
|
|
}
|
2013-09-25 12:12:48 +00:00
|
|
|
|
|
|
|
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
2017-10-13 04:28:50 +00:00
|
|
|
bool set_cpu_frequency__lock(void)
|
|
|
|
{
|
|
|
|
if (get_processor_mode() != CPU_MODE_THREAD_CONTEXT)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
mutex_lock(&cpufreq_mtx);
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
void set_cpu_frequency__unlock(void)
|
|
|
|
{
|
|
|
|
mutex_unlock(&cpufreq_mtx);
|
|
|
|
}
|
|
|
|
|
2013-09-25 12:12:48 +00:00
|
|
|
void set_cpu_frequency(long frequency)
|
|
|
|
{
|
|
|
|
return imx233_set_cpu_frequency(frequency);
|
|
|
|
}
|
2011-06-30 17:31:40 +00:00
|
|
|
#endif
|
2011-09-14 11:50:06 +00:00
|
|
|
|
|
|
|
void imx233_enable_usb_controller(bool enable)
|
|
|
|
{
|
|
|
|
if(enable)
|
2013-06-16 15:56:10 +00:00
|
|
|
BF_CLR(DIGCTL_CTRL, USB_CLKGATE);
|
2011-09-14 11:50:06 +00:00
|
|
|
else
|
2013-06-16 15:56:10 +00:00
|
|
|
BF_SET(DIGCTL_CTRL, USB_CLKGATE);
|
2011-09-14 11:50:06 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void imx233_enable_usb_phy(bool enable)
|
|
|
|
{
|
|
|
|
if(enable)
|
|
|
|
{
|
2013-06-16 15:56:10 +00:00
|
|
|
BF_CLR(USBPHY_CTRL, SFTRST);
|
|
|
|
BF_CLR(USBPHY_CTRL, CLKGATE);
|
|
|
|
HW_USBPHY_PWD_CLR = 0xffffffff;
|
2011-09-14 11:50:06 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
2013-06-16 15:56:10 +00:00
|
|
|
HW_USBPHY_PWD_SET = 0xffffffff;
|
|
|
|
BF_SET(USBPHY_CTRL, SFTRST);
|
|
|
|
BF_SET(USBPHY_CTRL, CLKGATE);
|
2011-09-14 11:50:06 +00:00
|
|
|
}
|
|
|
|
}
|