2005-03-18 11:39:28 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "config.h"
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#include "debug.h"
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#include "panic.h"
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#include <kernel.h>
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#include "cpu.h"
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#include "i2c.h"
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2005-08-06 10:12:19 +00:00
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#if defined(HAVE_UDA1380)
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2005-03-18 11:39:28 +00:00
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#include "uda1380.h"
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2005-12-16 11:00:44 +00:00
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#elif defined(HAVE_WM8975)
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#include "wm8975.h"
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2006-02-13 13:48:08 +00:00
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#elif defined(HAVE_WM8758)
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#include "wm8758.h"
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2005-08-06 10:12:19 +00:00
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#elif defined(HAVE_TLV320)
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#include "tlv320.h"
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2006-02-26 15:59:46 +00:00
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#elif defined(HAVE_WM8731)
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2006-02-05 17:34:49 +00:00
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#include "wm8731l.h"
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2005-08-06 10:12:19 +00:00
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#endif
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2005-03-18 11:39:28 +00:00
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#include "system.h"
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2005-06-19 18:41:53 +00:00
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#include "logf.h"
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2005-03-18 11:39:28 +00:00
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#include <stdio.h>
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#include <string.h>
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#include <stdarg.h>
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2005-06-05 23:05:10 +00:00
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#include "pcm_playback.h"
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2005-03-18 11:39:28 +00:00
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#include "lcd.h"
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#include "button.h"
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#include "file.h"
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#include "buffer.h"
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2005-03-28 00:00:24 +00:00
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#include "sprintf.h"
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#include "button.h"
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#include <string.h>
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2005-06-18 22:23:54 +00:00
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#ifdef HAVE_UDA1380
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-08-21 17:34:56 +00:00
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#define EBU_DEFPARM ((7 << 12) | (3 << 8) | (1 << 5) | (5 << 2))
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2005-11-27 01:11:25 +00:00
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#endif
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2005-08-21 17:34:56 +00:00
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#define IIS_DEFPARM(freq) ((freq << 12) | 0x300 | 4 << 2)
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#define IIS_RESET 0x800
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2005-03-28 00:00:24 +00:00
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static bool pcm_playing;
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2005-03-31 06:49:10 +00:00
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static bool pcm_paused;
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static int pcm_freq = 0x6; /* 44.1 is default */
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2005-03-18 11:39:28 +00:00
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2006-02-07 20:38:55 +00:00
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size_t next_size IBSS_ATTR;
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unsigned char *next_start IBSS_ATTR;
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2005-06-05 23:05:10 +00:00
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2005-03-18 11:39:28 +00:00
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/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
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2006-02-07 20:38:55 +00:00
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static void dma_start(const void *addr, size_t size)
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2005-03-31 06:49:10 +00:00
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{
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pcm_playing = true;
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2005-03-18 11:39:28 +00:00
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2005-03-31 06:49:10 +00:00
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addr = (void *)((unsigned long)addr & ~3); /* Align data */
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size &= ~3; /* Size must be multiple of 4 */
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2005-03-18 11:39:28 +00:00
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2005-03-31 06:49:10 +00:00
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/* Reset the audio FIFO */
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-12-27 18:00:45 +00:00
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EBU1CONFIG = IIS_RESET | EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-07-01 17:05:09 +00:00
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2005-03-18 11:39:28 +00:00
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/* Set up DMA transfer */
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2005-03-31 06:49:10 +00:00
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SAR0 = ((unsigned long)addr); /* Source address */
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DAR0 = (unsigned long)&PDOR3; /* Destination address */
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BCR0 = size; /* Bytes to transfer */
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2005-03-18 11:39:28 +00:00
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2005-03-31 06:49:10 +00:00
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/* Enable the FIFO and force one write to it */
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_DEFPARM(pcm_freq);
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2005-07-01 07:55:19 +00:00
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/* Also send the audio to S/PDIF */
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-08-21 17:34:56 +00:00
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EBU1CONFIG = EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-03-31 06:49:10 +00:00
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START;
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2005-03-18 11:39:28 +00:00
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}
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2005-06-10 10:58:45 +00:00
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/* Stops the DMA transfer and interrupt */
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static void dma_stop(void)
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{
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pcm_playing = false;
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2005-06-30 20:02:56 +00:00
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DCR0 = 0;
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2005-12-06 09:09:21 +00:00
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DSR0 = 1;
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2005-06-10 10:58:45 +00:00
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/* Reset the FIFO */
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-12-27 18:00:45 +00:00
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EBU1CONFIG = IIS_RESET | EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-07-07 07:15:05 +00:00
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2005-07-01 17:05:09 +00:00
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pcm_paused = false;
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2005-06-10 10:58:45 +00:00
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}
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2005-03-28 00:00:24 +00:00
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/* sets frequency of input to DAC */
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void pcm_set_frequency(unsigned int frequency)
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{
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2005-03-31 06:49:10 +00:00
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switch(frequency)
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{
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2005-03-28 00:00:24 +00:00
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case 11025:
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pcm_freq = 0x4;
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2005-07-01 07:55:19 +00:00
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uda1380_set_nsorder(3);
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2005-03-28 00:00:24 +00:00
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break;
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2005-07-01 07:55:19 +00:00
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case 22050:
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2005-03-28 00:00:24 +00:00
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pcm_freq = 0x6;
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2005-07-01 07:55:19 +00:00
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uda1380_set_nsorder(3);
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2005-03-28 00:00:24 +00:00
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break;
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2005-07-01 07:55:19 +00:00
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case 44100:
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2005-03-28 00:00:24 +00:00
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default:
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2005-07-01 07:55:19 +00:00
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pcm_freq = 0xC;
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uda1380_set_nsorder(5);
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2005-03-31 06:49:10 +00:00
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break;
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}
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2005-03-28 00:00:24 +00:00
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}
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2005-03-18 11:39:28 +00:00
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/* the registered callback function to ask for more mp3 data */
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2006-02-07 20:38:55 +00:00
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static void (*callback_for_more)(unsigned char**, size_t*) IDATA_ATTR = NULL;
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2005-03-18 11:39:28 +00:00
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2006-02-07 20:38:55 +00:00
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void pcm_play_data(void (*get_more)(unsigned char** start, size_t* size),
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unsigned char* start, size_t size)
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2005-06-05 23:05:10 +00:00
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{
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2005-03-18 11:39:28 +00:00
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callback_for_more = get_more;
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2005-08-06 10:12:19 +00:00
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2006-02-07 20:38:55 +00:00
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if (!(start && size))
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{
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if (get_more)
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get_more(&start, &size);
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else
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return;
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}
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if (start && size)
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dma_start(start, size);
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2005-03-18 11:39:28 +00:00
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}
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2006-02-07 20:38:55 +00:00
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size_t pcm_get_bytes_waiting(void)
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2005-07-22 06:32:55 +00:00
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{
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2006-02-07 20:38:55 +00:00
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return (BCR0 & 0xffffff);
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2005-07-22 06:32:55 +00:00
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}
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2006-01-22 10:25:07 +00:00
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void pcm_mute(bool mute)
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{
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uda1380_mute(mute);
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if (mute)
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sleep(HZ/16);
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}
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2005-03-18 11:39:28 +00:00
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void pcm_play_stop(void)
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{
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2005-06-14 09:25:28 +00:00
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if (pcm_playing) {
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2005-06-14 07:54:09 +00:00
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dma_stop();
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2005-06-14 09:25:28 +00:00
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}
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2005-03-18 11:39:28 +00:00
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}
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2005-03-31 06:49:10 +00:00
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void pcm_play_pause(bool play)
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{
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2006-01-20 22:02:44 +00:00
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if (!pcm_playing)
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return ;
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2006-02-07 20:38:55 +00:00
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if(pcm_paused && play)
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2005-03-31 06:49:10 +00:00
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{
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2006-02-07 20:38:55 +00:00
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if (BCR0 & 0xffffff)
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{
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logf("unpause");
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/* Enable the FIFO and force one write to it */
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IIS2CONFIG = IIS_DEFPARM(pcm_freq);
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2006-02-07 20:38:55 +00:00
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EBU1CONFIG = EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2006-02-07 20:38:55 +00:00
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DCR0 |= DMA_EEXT | DMA_START;
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}
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else
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{
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logf("unpause, no data waiting");
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void (*get_more)(unsigned char**, size_t*) = callback_for_more;
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if (get_more)
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get_more(&next_start, &next_size);
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if (next_start && next_size)
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dma_start(next_start, next_size);
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else
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{
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dma_stop();
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logf("unpause attempted, no data");
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}
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}
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2005-03-31 06:49:10 +00:00
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}
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else if(!pcm_paused && !play)
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{
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2005-06-30 20:02:56 +00:00
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logf("pause");
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2005-08-06 10:12:19 +00:00
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2005-06-30 20:02:56 +00:00
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/* Disable DMA peripheral request. */
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DCR0 &= ~DMA_EEXT;
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-12-27 18:00:45 +00:00
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EBU1CONFIG = IIS_RESET | EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-03-31 06:49:10 +00:00
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}
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2005-06-10 20:46:39 +00:00
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pcm_paused = !play;
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2005-03-31 06:49:10 +00:00
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}
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2005-07-13 12:48:22 +00:00
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bool pcm_is_paused(void)
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{
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return pcm_paused;
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}
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2005-03-18 11:39:28 +00:00
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bool pcm_is_playing(void)
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{
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return pcm_playing;
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}
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/* DMA0 Interrupt is called when the DMA has finished transfering a chunk */
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void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA0(void)
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{
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2005-03-28 00:00:24 +00:00
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int res = DSR0;
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2005-03-18 11:39:28 +00:00
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DSR0 = 1; /* Clear interrupt */
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2005-07-01 17:05:09 +00:00
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DCR0 &= ~DMA_EEXT;
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2005-08-06 10:12:19 +00:00
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2005-03-31 06:49:10 +00:00
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/* Stop on error */
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if(res & 0x70)
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2005-03-28 00:00:24 +00:00
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{
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2006-01-21 22:35:42 +00:00
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dma_stop();
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2005-07-07 07:15:05 +00:00
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logf("DMA Error:0x%04x", res);
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2005-03-28 00:00:24 +00:00
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}
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2005-03-18 11:39:28 +00:00
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else
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{
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2006-02-07 20:38:55 +00:00
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{
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void (*get_more)(unsigned char**, size_t*) = callback_for_more;
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if (get_more)
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get_more(&next_start, &next_size);
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else
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{
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next_size = 0;
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next_start = NULL;
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}
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}
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2005-06-05 23:05:10 +00:00
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if(next_size)
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2005-03-31 06:49:10 +00:00
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{
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2005-06-05 23:05:10 +00:00
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SAR0 = (unsigned long)next_start; /* Source address */
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BCR0 = next_size; /* Bytes to transfer */
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2005-07-01 17:05:09 +00:00
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DCR0 |= DMA_EEXT;
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2006-02-07 20:38:55 +00:00
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2005-03-31 06:49:10 +00:00
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}
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else
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{
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/* Finished playing */
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2006-01-21 22:35:42 +00:00
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dma_stop();
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2005-07-07 07:15:05 +00:00
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logf("DMA No Data:0x%04x", res);
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2005-03-31 06:49:10 +00:00
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}
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2005-03-18 11:39:28 +00:00
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}
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2005-08-06 10:12:19 +00:00
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2005-03-18 11:39:28 +00:00
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IPR |= (1<<14); /* Clear pending interrupt request */
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}
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2005-03-31 06:49:10 +00:00
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void pcm_init(void)
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{
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pcm_playing = false;
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pcm_paused = false;
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2005-08-06 10:12:19 +00:00
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2005-11-05 03:28:20 +00:00
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MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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2005-03-31 06:49:10 +00:00
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DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1;
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DMACONFIG = 1; /* DMA0Req = PDOR3 */
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/* Reset the audio FIFO */
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_RESET;
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2005-08-06 10:12:19 +00:00
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2005-03-31 06:49:10 +00:00
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/* Enable interrupt at level 7, priority 0 */
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2005-11-05 03:28:20 +00:00
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ICR6 = 0x1c;
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2005-03-31 06:49:10 +00:00
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|
|
IMR &= ~(1<<14); /* bit 14 is DMA0 */
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-03-31 06:49:10 +00:00
|
|
|
pcm_set_frequency(44100);
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-08-21 17:34:56 +00:00
|
|
|
/* Prevent pops (resets DAC to zero point) */
|
|
|
|
IIS2CONFIG = IIS_DEFPARM(pcm_freq) | IIS_RESET;
|
|
|
|
|
2005-08-06 10:12:19 +00:00
|
|
|
#if defined(HAVE_UDA1380)
|
2005-08-21 17:34:56 +00:00
|
|
|
/* Initialize default register values. */
|
|
|
|
uda1380_init();
|
|
|
|
|
2005-08-28 15:33:37 +00:00
|
|
|
/* Sleep a while so the power can stabilize (especially a long
|
|
|
|
delay is needed for the line out connector). */
|
|
|
|
sleep(HZ);
|
2005-08-21 17:34:56 +00:00
|
|
|
|
2005-08-28 15:33:37 +00:00
|
|
|
/* Power on FSDAC and HP amp. */
|
|
|
|
uda1380_enable_output(true);
|
2005-08-21 17:34:56 +00:00
|
|
|
|
|
|
|
/* Unmute the master channel (DAC should be at zero point now). */
|
|
|
|
uda1380_mute(false);
|
2005-08-28 15:33:37 +00:00
|
|
|
|
2005-08-06 10:12:19 +00:00
|
|
|
#elif defined(HAVE_TLV320)
|
2005-08-21 17:34:56 +00:00
|
|
|
tlv320_init();
|
2005-08-06 10:12:19 +00:00
|
|
|
tlv320_enable_output(true);
|
2005-08-21 17:34:56 +00:00
|
|
|
sleep(HZ/4);
|
|
|
|
tlv320_mute(false);
|
2005-08-06 10:12:19 +00:00
|
|
|
#endif
|
2005-08-21 17:34:56 +00:00
|
|
|
|
2005-07-07 07:15:05 +00:00
|
|
|
/* Call dma_stop to initialize everything. */
|
|
|
|
dma_stop();
|
2005-04-14 11:51:31 +00:00
|
|
|
}
|
2005-06-18 22:23:54 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif defined(HAVE_WM8975) || defined(HAVE_WM8758) || defined(HAVE_WM8731)
|
2005-11-12 15:29:43 +00:00
|
|
|
|
2005-12-16 11:00:44 +00:00
|
|
|
/* We need to unify this code with the uda1380 code as much as possible, but
|
|
|
|
we will keep it separate during early development.
|
2005-11-12 15:29:43 +00:00
|
|
|
*/
|
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
#define FIFO_FREE_COUNT ((IISFIFO_CFG & 0x3f0000) >> 16)
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
|
|
|
#define FIFO_FREE_COUNT ((IISFIFO_CFG & 0x7800000) >> 23)
|
|
|
|
#endif
|
2006-02-07 20:49:13 +00:00
|
|
|
|
2005-12-16 11:00:44 +00:00
|
|
|
static bool pcm_playing;
|
|
|
|
static bool pcm_paused;
|
|
|
|
static int pcm_freq = 0x6; /* 44.1 is default */
|
|
|
|
|
2006-03-05 21:16:57 +00:00
|
|
|
/* NOTE: The order of these two variables is important if you use the iPod
|
|
|
|
assembler optimised fiq handler, so don't change it. */
|
2006-02-07 20:49:13 +00:00
|
|
|
unsigned short* p IBSS_ATTR;
|
|
|
|
long p_size IBSS_ATTR;
|
2005-12-16 11:00:44 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
static void dma_start(const void *addr, size_t size)
|
2005-11-12 15:29:43 +00:00
|
|
|
{
|
2006-02-07 20:49:13 +00:00
|
|
|
p=(unsigned short*)addr;
|
|
|
|
p_size=size;
|
2005-11-12 15:29:43 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
pcm_playing = true;
|
2005-11-12 15:29:43 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
/* setup I2S interrupt for FIQ */
|
|
|
|
outl(inl(0x6000402c) | I2S_MASK, 0x6000402c);
|
|
|
|
outl(I2S_MASK, 0x60004024);
|
2006-02-26 15:59:46 +00:00
|
|
|
#else
|
|
|
|
/* setup I2S interrupt for FIQ */
|
2006-02-26 20:29:29 +00:00
|
|
|
outl(inl(0xcf00103c) | DMA_OUT_MASK, 0xcf00103c);
|
|
|
|
outl(DMA_OUT_MASK, 0xcf001034);
|
2006-02-26 15:59:46 +00:00
|
|
|
#endif
|
2005-11-12 15:29:43 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Clear the FIQ disable bit in cpsr_c */
|
|
|
|
enable_fiq();
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Enable playback FIFO */
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
IISCONFIG |= 0x20000000;
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
|
|
|
IISCONFIG |= 0x4;
|
|
|
|
#endif
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Fill the FIFO - we assume there are enough bytes in the pcm buffer to
|
|
|
|
fill the 32-byte FIFO. */
|
|
|
|
while (p_size > 0) {
|
|
|
|
if (FIFO_FREE_COUNT < 2) {
|
2006-01-28 20:33:57 +00:00
|
|
|
/* Enable interrupt */
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-01-28 20:33:57 +00:00
|
|
|
IISCONFIG |= 0x2;
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
2006-02-26 20:29:29 +00:00
|
|
|
IISFIFO_CFG |= (1<<9);
|
2006-02-26 15:59:46 +00:00
|
|
|
#endif
|
2006-01-28 20:33:57 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
IISFIFO_WR = (*(p++))<<16;
|
|
|
|
IISFIFO_WR = (*(p++))<<16;
|
2006-02-07 20:49:13 +00:00
|
|
|
p_size-=4;
|
2006-01-28 20:33:57 +00:00
|
|
|
}
|
|
|
|
}
|
2005-12-16 11:00:44 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Stops the DMA transfer and interrupt */
|
|
|
|
static void dma_stop(void)
|
2005-11-12 15:29:43 +00:00
|
|
|
{
|
2006-02-07 20:49:13 +00:00
|
|
|
pcm_playing = false;
|
2005-12-16 11:00:44 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Disable playback FIFO */
|
|
|
|
IISCONFIG &= ~0x20000000;
|
2005-12-16 11:00:44 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Disable the interrupt */
|
|
|
|
IISCONFIG &= ~0x2;
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
|
|
|
|
|
|
|
/* Disable playback FIFO */
|
|
|
|
IISCONFIG &= ~0x4;
|
|
|
|
|
|
|
|
/* Disable the interrupt */
|
|
|
|
IISFIFO_CFG &= ~(1<<9);
|
|
|
|
#endif
|
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
disable_fiq();
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
pcm_paused = false;
|
|
|
|
}
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
void pcm_set_frequency(unsigned int frequency)
|
|
|
|
{
|
|
|
|
pcm_freq=frequency;
|
|
|
|
}
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* the registered callback function to ask for more PCM data */
|
|
|
|
static void (*callback_for_more)(unsigned char**, size_t*) IDATA_ATTR = NULL;
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
void pcm_play_data(void (*get_more)(unsigned char** start, size_t* size),
|
|
|
|
unsigned char* start, size_t size)
|
|
|
|
{
|
|
|
|
callback_for_more = get_more;
|
|
|
|
|
|
|
|
if (!(start && size))
|
|
|
|
{
|
|
|
|
if (get_more)
|
|
|
|
get_more(&start, &size);
|
|
|
|
else
|
2006-01-28 20:33:57 +00:00
|
|
|
return;
|
2006-02-07 20:49:13 +00:00
|
|
|
}
|
|
|
|
if (start && size)
|
|
|
|
dma_start(start, size);
|
|
|
|
}
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
size_t pcm_get_bytes_waiting(void)
|
|
|
|
{
|
|
|
|
return p_size;
|
|
|
|
}
|
2006-01-28 20:33:57 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
void pcm_mute(bool mute)
|
|
|
|
{
|
2006-02-13 13:48:08 +00:00
|
|
|
wmcodec_mute(mute);
|
2006-02-07 20:49:13 +00:00
|
|
|
if (mute)
|
|
|
|
sleep(HZ/16);
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_stop(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
if (pcm_playing) {
|
|
|
|
dma_stop();
|
|
|
|
}
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_pause(bool play)
|
|
|
|
{
|
2006-02-07 20:49:13 +00:00
|
|
|
size_t next_size;
|
|
|
|
unsigned char *next_start;
|
|
|
|
|
|
|
|
if (!pcm_playing)
|
|
|
|
return ;
|
|
|
|
|
|
|
|
if(pcm_paused && play)
|
2005-12-16 11:00:44 +00:00
|
|
|
{
|
2006-02-07 20:49:13 +00:00
|
|
|
if (pcm_get_bytes_waiting())
|
|
|
|
{
|
|
|
|
logf("unpause");
|
|
|
|
/* Enable the FIFO and fill it */
|
|
|
|
|
|
|
|
enable_fiq();
|
|
|
|
|
|
|
|
/* Enable playback FIFO */
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
IISCONFIG |= 0x20000000;
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
|
|
|
IISCONFIG |= 0x4;
|
|
|
|
#endif
|
2006-02-07 20:49:13 +00:00
|
|
|
|
|
|
|
/* Fill the FIFO - we assume there are enough bytes in the
|
|
|
|
pcm buffer to fill the 32-byte FIFO. */
|
|
|
|
while (p_size > 0) {
|
|
|
|
if (FIFO_FREE_COUNT < 2) {
|
|
|
|
/* Enable interrupt */
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
IISCONFIG |= 0x2;
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
2006-02-26 20:29:29 +00:00
|
|
|
IISFIFO_CFG |= (1<<9);
|
2006-02-26 15:59:46 +00:00
|
|
|
#endif
|
2006-02-07 20:49:13 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
IISFIFO_WR = (*(p++))<<16;
|
|
|
|
IISFIFO_WR = (*(p++))<<16;
|
|
|
|
p_size-=4;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
logf("unpause, no data waiting");
|
|
|
|
void (*get_more)(unsigned char**, size_t*) = callback_for_more;
|
|
|
|
if (get_more)
|
|
|
|
get_more(&next_start, &next_size);
|
|
|
|
if (next_start && next_size)
|
|
|
|
dma_start(next_start, next_size);
|
|
|
|
else
|
|
|
|
{
|
|
|
|
dma_stop();
|
|
|
|
logf("unpause attempted, no data");
|
|
|
|
}
|
|
|
|
}
|
2005-12-16 11:00:44 +00:00
|
|
|
}
|
|
|
|
else if(!pcm_paused && !play)
|
|
|
|
{
|
|
|
|
logf("pause");
|
2006-02-07 20:49:13 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Disable the interrupt */
|
|
|
|
IISCONFIG &= ~0x2;
|
|
|
|
|
|
|
|
/* Disable playback FIFO */
|
|
|
|
IISCONFIG &= ~0x20000000;
|
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
|
|
|
|
|
|
|
/* Disable the interrupt */
|
|
|
|
IISFIFO_CFG &= ~(1<<9);
|
|
|
|
|
|
|
|
/* Disable playback FIFO */
|
|
|
|
IISCONFIG &= ~0x4;
|
|
|
|
#endif
|
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
disable_fiq();
|
2005-12-16 11:00:44 +00:00
|
|
|
}
|
|
|
|
pcm_paused = !play;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_paused(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
return pcm_paused;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_playing(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
return pcm_playing;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
2006-02-19 00:57:27 +00:00
|
|
|
/* ASM optimised FIQ handler. GCC fails to make use of the fact that FIQ mode
|
|
|
|
has registers r8-r14 banked, and so does not need to be saved. This routine
|
|
|
|
uses only these registers, and so will never touch the stack unless it
|
|
|
|
actually needs to do so when calling callback_for_more. C version is still
|
|
|
|
included below for reference.
|
|
|
|
*/
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-19 00:57:27 +00:00
|
|
|
void fiq(void) ICODE_ATTR __attribute__((naked));
|
|
|
|
void fiq(void)
|
|
|
|
{
|
2006-03-05 21:16:57 +00:00
|
|
|
/* r12 contains IISCONFIG address (set in crt0.S to minimise code in actual
|
|
|
|
* FIQ handler. r11 contains address of p (also set in crt0.S). Most other
|
|
|
|
* addresses we need are generated by using offsets with these two.
|
|
|
|
* r12 + 0x40 is IISFIFO_WR, and r12 + 0x0c is IISFIFO_CFG.
|
|
|
|
* r8 and r9 contains local copies of p_size and p respectively.
|
|
|
|
* r10 is a working register.
|
|
|
|
*/
|
2006-02-19 00:57:27 +00:00
|
|
|
asm volatile (
|
2006-03-05 21:16:57 +00:00
|
|
|
"ldr r10, [r12] \n\t"
|
|
|
|
"bic r10, r10, #0x2 \n\t" /* clear interrupt */
|
|
|
|
"str r10, [r12] \n\t"
|
|
|
|
"ldr r8, [r11, #4] \n\t" /* r8 = p_size */
|
|
|
|
"ldr r9, [r11] \n\t" /* r9 = p */
|
2006-02-19 00:57:27 +00:00
|
|
|
".loop: \n\t"
|
|
|
|
"cmp r8, #0 \n\t" /* is p_size 0? */
|
|
|
|
"beq .more_data \n\t" /* if so, ask pcmbuf for more data */
|
|
|
|
".fifo_loop: \n\t"
|
2006-03-05 21:16:57 +00:00
|
|
|
"ldr r10, [r12, #0x0c]\n\t" /* read IISFIFO_CFG to check FIFO status */
|
|
|
|
"and r10, r10, #0x3f0000\n\t"
|
|
|
|
"cmp r10, #0x10000 \n\t"
|
2006-02-19 00:57:27 +00:00
|
|
|
"bls .fifo_full \n\t" /* FIFO full, exit */
|
2006-03-05 21:16:57 +00:00
|
|
|
"ldr r10, [r9], #4 \n\t" /* load two samples */
|
|
|
|
"mov r10, r10, ror #16\n\t" /* put left sample at the top bits */
|
|
|
|
"str r10, [r12, #0x40]\n\t" /* write top sample, lower sample ignored */
|
|
|
|
"mov r10, r10, lsl #16\n\t" /* shift lower sample up */
|
|
|
|
"str r10, [r12, #0x40]\n\t" /* then write it */
|
2006-02-19 00:57:27 +00:00
|
|
|
"subs r8, r8, #4 \n\t" /* check if we have more samples */
|
2006-02-20 20:23:21 +00:00
|
|
|
"bne .fifo_loop \n\t" /* yes, continue */
|
2006-02-19 00:57:27 +00:00
|
|
|
".more_data: \n\t"
|
2006-03-05 21:16:57 +00:00
|
|
|
"stmdb sp!, { r0-r3, r12, lr}\n\t" /* stack scratch regs and lr */
|
|
|
|
"mov r0, r11 \n\t" /* r0 = &p */
|
|
|
|
"add r1, r11, #4 \n\t" /* r1 = &p_size */
|
2006-02-19 00:57:27 +00:00
|
|
|
"str r9, [r0] \n\t" /* save internal copies of variables back */
|
|
|
|
"str r8, [r1] \n\t"
|
|
|
|
"ldr r2, =callback_for_more\n\t"
|
|
|
|
"ldr r2, [r2] \n\t" /* get callback address */
|
|
|
|
"cmp r2, #0 \n\t" /* check for null pointer */
|
|
|
|
"movne lr, pc \n\t" /* call callback_for_more */
|
|
|
|
"bxne r2 \n\t"
|
2006-03-05 21:16:57 +00:00
|
|
|
"ldmia sp!, { r0-r3, r12, lr}\n\t"
|
|
|
|
"ldr r8, [r11, #4] \n\t" /* reload p_size and p */
|
|
|
|
"ldr r9, [r11] \n\t"
|
2006-02-19 00:57:27 +00:00
|
|
|
"cmp r8, #0 \n\t" /* did we actually get more data? */
|
|
|
|
"bne .loop \n\t" /* yes, continue to try feeding FIFO */
|
|
|
|
".dma_stop: \n\t" /* no more data, do dma_stop() and exit */
|
|
|
|
"ldr r10, =pcm_playing\n\t"
|
2006-02-23 11:31:55 +00:00
|
|
|
"strb r8, [r10] \n\t" /* pcm_playing = false (r8=0, look above) */
|
2006-03-05 21:16:57 +00:00
|
|
|
"ldr r10, [r12] \n\t"
|
|
|
|
"bic r10, r10, #0x20000002\n\t" /* disable playback FIFO and IRQ */
|
|
|
|
"str r10, [r12] \n\t"
|
2006-02-19 00:57:27 +00:00
|
|
|
"mrs r10, cpsr \n\t"
|
|
|
|
"orr r10, r10, #0x40 \n\t" /* disable FIQ */
|
|
|
|
"msr cpsr_c, r10 \n\t"
|
|
|
|
"ldr r10, =pcm_paused \n\t"
|
2006-02-23 11:31:55 +00:00
|
|
|
"strb r8, [r10] \n\t" /* pcm_paused = false */
|
2006-02-19 00:57:27 +00:00
|
|
|
".exit: \n\t"
|
2006-03-05 21:16:57 +00:00
|
|
|
"str r8, [r11, #4] \n\t"
|
2006-02-19 00:57:27 +00:00
|
|
|
"str r9, [r11] \n\t"
|
|
|
|
"subs pc, lr, #4 \n\t" /* FIQ specific return sequence */
|
|
|
|
".fifo_full: \n\t" /* enable IRQ and exit */
|
2006-03-05 21:16:57 +00:00
|
|
|
"ldr r10, [r12] \n\t"
|
|
|
|
"orr r10, r10, #0x2 \n\t" /* set interrupt */
|
|
|
|
"str r10, [r12] \n\t"
|
2006-02-19 00:57:27 +00:00
|
|
|
"b .exit \n\t"
|
|
|
|
);
|
|
|
|
}
|
|
|
|
#else
|
|
|
|
void fiq(void) ICODE_ATTR __attribute__ ((interrupt ("FIQ")));
|
2006-02-07 20:49:13 +00:00
|
|
|
void fiq(void)
|
2006-02-05 17:34:49 +00:00
|
|
|
{
|
2006-02-07 20:49:13 +00:00
|
|
|
/* Clear interrupt */
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
IISCONFIG &= ~0x2;
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
|
|
|
inl(0xcf001040);
|
|
|
|
IISFIFO_CFG &= ~(1<<9);
|
|
|
|
#endif
|
2006-02-05 17:34:49 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
do {
|
|
|
|
while (p_size) {
|
|
|
|
if (FIFO_FREE_COUNT < 2) {
|
|
|
|
/* Enable interrupt */
|
2006-02-26 15:59:46 +00:00
|
|
|
#if CONFIG_CPU == PP5020
|
2006-02-07 20:49:13 +00:00
|
|
|
IISCONFIG |= 0x2;
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif CONFIG_CPU == PP5002
|
2006-02-26 20:29:29 +00:00
|
|
|
IISFIFO_CFG |= (1<<9);
|
2006-02-26 15:59:46 +00:00
|
|
|
#endif
|
2006-02-07 20:49:13 +00:00
|
|
|
return;
|
|
|
|
}
|
2006-02-05 17:34:49 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
IISFIFO_WR = (*(p++))<<16;
|
|
|
|
IISFIFO_WR = (*(p++))<<16;
|
|
|
|
p_size-=4;
|
|
|
|
}
|
2006-02-05 17:34:49 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* p is empty, get some more data */
|
|
|
|
if (callback_for_more) {
|
|
|
|
callback_for_more((unsigned char**)&p,&p_size);
|
|
|
|
}
|
|
|
|
} while (p_size);
|
2006-02-05 17:34:49 +00:00
|
|
|
|
2006-02-07 20:49:13 +00:00
|
|
|
/* No more data, so disable the FIFO/FIQ */
|
|
|
|
dma_stop();
|
2006-02-05 17:34:49 +00:00
|
|
|
}
|
2006-02-19 00:57:27 +00:00
|
|
|
#endif
|
2006-02-05 17:34:49 +00:00
|
|
|
|
|
|
|
void pcm_init(void)
|
|
|
|
{
|
|
|
|
pcm_playing = false;
|
|
|
|
pcm_paused = false;
|
|
|
|
|
|
|
|
/* Initialize default register values. */
|
2006-02-13 13:48:08 +00:00
|
|
|
wmcodec_init();
|
2006-02-05 17:34:49 +00:00
|
|
|
|
|
|
|
/* The uda1380 needs a sleep(HZ) here - do we need one? */
|
|
|
|
|
|
|
|
/* Power on */
|
2006-02-13 13:48:08 +00:00
|
|
|
wmcodec_enable_output(true);
|
2006-02-05 17:34:49 +00:00
|
|
|
|
|
|
|
/* Unmute the master channel (DAC should be at zero point now). */
|
2006-02-13 13:48:08 +00:00
|
|
|
wmcodec_mute(false);
|
2006-02-07 20:49:13 +00:00
|
|
|
|
2006-02-05 17:34:49 +00:00
|
|
|
/* Call dma_stop to initialize everything. */
|
|
|
|
dma_stop();
|
|
|
|
}
|
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif (CONFIG_CPU == PNX0101)
|
2006-01-12 00:35:50 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
/* TODO: Implement for iFP7xx
|
2006-01-12 00:35:50 +00:00
|
|
|
For now, just implement some dummy functions.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void pcm_init(void)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_set_frequency(unsigned int frequency)
|
|
|
|
{
|
|
|
|
(void)frequency;
|
|
|
|
}
|
|
|
|
|
2006-02-12 23:26:18 +00:00
|
|
|
void pcm_play_data(void (*get_more)(unsigned char** start, size_t* size),
|
|
|
|
unsigned char* start, size_t size)
|
2006-01-12 00:35:50 +00:00
|
|
|
{
|
|
|
|
(void)get_more;
|
2006-02-07 20:38:55 +00:00
|
|
|
(void)start;
|
|
|
|
(void)size;
|
2006-01-12 00:35:50 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_stop(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
2006-01-22 11:56:08 +00:00
|
|
|
void pcm_mute(bool mute)
|
|
|
|
{
|
|
|
|
(void)mute;
|
|
|
|
}
|
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
void pcm_play_pause(bool play)
|
|
|
|
{
|
|
|
|
(void)play;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_paused(void)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_playing(void)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_calculate_peaks(int *left, int *right)
|
|
|
|
{
|
|
|
|
(void)left;
|
|
|
|
(void)right;
|
|
|
|
}
|
|
|
|
|
2006-02-12 23:26:18 +00:00
|
|
|
size_t pcm_get_bytes_waiting(void)
|
2006-01-12 00:35:50 +00:00
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-12 15:29:43 +00:00
|
|
|
#endif
|
2006-02-01 00:17:36 +00:00
|
|
|
|
2006-02-26 15:59:46 +00:00
|
|
|
#if (CONFIG_CPU != PNX0101)
|
2006-02-01 00:17:36 +00:00
|
|
|
/*
|
|
|
|
* This function goes directly into the DMA buffer to calculate the left and
|
|
|
|
* right peak values. To avoid missing peaks it tries to look forward two full
|
|
|
|
* peek periods (2/HZ sec, 100% overlap), although it's always possible that
|
|
|
|
* the entire period will not be visible. To reduce CPU load it only looks at
|
|
|
|
* every third sample, and this can be reduced even further if needed (even
|
|
|
|
* every tenth sample would still be pretty accurate).
|
|
|
|
*/
|
|
|
|
|
|
|
|
#define PEAK_SAMPLES (44100*2/HZ) /* 44100 samples * 2 / 100 Hz tick */
|
|
|
|
#define PEAK_STRIDE 3 /* every 3rd sample is plenty... */
|
|
|
|
|
|
|
|
void pcm_calculate_peaks(int *left, int *right)
|
|
|
|
{
|
|
|
|
#ifdef HAVE_UDA1380
|
|
|
|
long samples = (BCR0 & 0xffffff) / 4;
|
|
|
|
short *addr = (short *) (SAR0 & ~3);
|
2006-02-26 15:59:46 +00:00
|
|
|
#elif defined(HAVE_WM8975) || defined(HAVE_WM8758) || defined(HAVE_WM8731)
|
2006-02-07 20:49:13 +00:00
|
|
|
long samples = p_size / 4;
|
2006-02-01 00:17:36 +00:00
|
|
|
short *addr = p;
|
2006-02-04 00:01:15 +00:00
|
|
|
#elif defined(HAVE_TLV320)
|
|
|
|
long samples = 4; /* TODO X5 */
|
|
|
|
short *addr = NULL;
|
2006-02-01 00:17:36 +00:00
|
|
|
#endif
|
|
|
|
|
|
|
|
if (samples > PEAK_SAMPLES)
|
|
|
|
samples = PEAK_SAMPLES;
|
|
|
|
|
|
|
|
samples /= PEAK_STRIDE;
|
|
|
|
|
|
|
|
if (left && right) {
|
|
|
|
int left_peak = 0, right_peak = 0, value;
|
|
|
|
|
|
|
|
while (samples--) {
|
|
|
|
if ((value = addr [0]) > left_peak)
|
|
|
|
left_peak = value;
|
|
|
|
else if (-value > left_peak)
|
|
|
|
left_peak = -value;
|
|
|
|
|
|
|
|
if ((value = addr [PEAK_STRIDE | 1]) > right_peak)
|
|
|
|
right_peak = value;
|
|
|
|
else if (-value > right_peak)
|
|
|
|
right_peak = -value;
|
|
|
|
|
|
|
|
addr += PEAK_STRIDE * 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
*left = left_peak;
|
|
|
|
*right = right_peak;
|
|
|
|
}
|
|
|
|
else if (left || right) {
|
|
|
|
int peak_value = 0, value;
|
|
|
|
|
|
|
|
if (right)
|
|
|
|
addr += (PEAK_STRIDE | 1);
|
|
|
|
|
|
|
|
while (samples--) {
|
|
|
|
if ((value = addr [0]) > peak_value)
|
|
|
|
peak_value = value;
|
|
|
|
else if (-value > peak_value)
|
|
|
|
peak_value = -value;
|
|
|
|
|
|
|
|
addr += PEAK_STRIDE * 2;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (left)
|
|
|
|
*left = peak_value;
|
|
|
|
else
|
|
|
|
*right = peak_value;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#endif
|