Fixup of the MCF5249 memory mapped register definitions.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@7755 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Jens Arnold
parent
81411a8226
commit
72f98786a0
5 changed files with 39 additions and 27 deletions
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@ -22,14 +22,27 @@
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#define MBAR 0x40000000
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#define MBAR2 0x80000000
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#define SYSTEM_CTRL (*(volatile unsigned char *)(MBAR + 0x000))
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#define BUSMASTER_CTRL (*(volatile unsigned char *)(MBAR + 0x00c))
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#define RSR (*(volatile unsigned char *)(MBAR + 0x000))
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#define SYPCR (*(volatile unsigned char *)(MBAR + 0x001))
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#define SWIVR (*(volatile unsigned char *)(MBAR + 0x002))
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#define SWSR (*(volatile unsigned char *)(MBAR + 0x003))
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#define IPR (*(volatile unsigned long *)(MBAR + 0x040))
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#define IMR (*(volatile unsigned long *)(MBAR + 0x044))
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#define ICR0 (*(volatile unsigned long *)(MBAR + 0x04c))
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#define ICR4 (*(volatile unsigned long *)(MBAR + 0x050))
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#define ICR8 (*(volatile unsigned long *)(MBAR + 0x054))
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#define MPARK (*(volatile unsigned char *)(MBAR + 0x00c))
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#define IPR (*(volatile unsigned long *)(MBAR + 0x040))
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#define IMR (*(volatile unsigned long *)(MBAR + 0x044))
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#define ICR0 (*(volatile unsigned char *)(MBAR + 0x04c))
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#define ICR1 (*(volatile unsigned char *)(MBAR + 0x04d))
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#define ICR2 (*(volatile unsigned char *)(MBAR + 0x04e))
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#define ICR3 (*(volatile unsigned char *)(MBAR + 0x04f))
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#define ICR4 (*(volatile unsigned char *)(MBAR + 0x050))
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#define ICR5 (*(volatile unsigned char *)(MBAR + 0x051))
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#define ICR6 (*(volatile unsigned char *)(MBAR + 0x052))
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#define ICR7 (*(volatile unsigned char *)(MBAR + 0x053))
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#define ICR8 (*(volatile unsigned char *)(MBAR + 0x054))
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#define ICR9 (*(volatile unsigned char *)(MBAR + 0x055))
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#define ICR10 (*(volatile unsigned char *)(MBAR + 0x056))
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#define ICR11 (*(volatile unsigned char *)(MBAR + 0x057))
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#define CSAR0 (*(volatile unsigned long *)(MBAR + 0x080))
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#define CSMR0 (*(volatile unsigned long *)(MBAR + 0x084))
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@ -53,12 +66,12 @@
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#define TRR0 (*(volatile unsigned short *)(MBAR + 0x144))
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#define TCR0 (*(volatile unsigned short *)(MBAR + 0x148))
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#define TCN0 (*(volatile unsigned short *)(MBAR + 0x14c))
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#define TER0 (*(volatile unsigned short *)(MBAR + 0x150))
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#define TER0 (*(volatile unsigned char *)(MBAR + 0x151))
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#define TMR1 (*(volatile unsigned short *)(MBAR + 0x180))
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#define TRR1 (*(volatile unsigned short *)(MBAR + 0x184))
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#define TCR1 (*(volatile unsigned short *)(MBAR + 0x188))
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#define TCN1 (*(volatile unsigned short *)(MBAR + 0x18c))
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#define TER1 (*(volatile unsigned short *)(MBAR + 0x190))
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#define TER1 (*(volatile unsigned char *)(MBAR + 0x191))
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#define UMR0 (*(volatile unsigned char *)(MBAR + 0x1c0))
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#define USR0 (*(volatile unsigned char *)(MBAR + 0x1c4))
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@ -133,11 +146,11 @@
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#define QSPIQWR (*(volatile unsigned short *)(MBAR + 0x408))
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#define QSPIQIR (*(volatile unsigned short *)(MBAR + 0x40c))
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#define QSPIQAR (*(volatile unsigned short *)(MBAR + 0x410))
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#define QIR (*(volatile unsigned short *)(MBAR + 0x414))
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#define QSPIQDR (*(volatile unsigned short *)(MBAR + 0x414))
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#define GPIO_READ (*(volatile unsigned long *)(MBAR2 + 0x000))
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#define GPIO_OUT (*(volatile unsigned long *)(MBAR2 + 0x004))
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#define GPIO_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x008))
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#define GPIO_READ (*(volatile unsigned long *)(MBAR2 + 0x000))
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#define GPIO_OUT (*(volatile unsigned long *)(MBAR2 + 0x004))
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#define GPIO_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x008))
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#define GPIO_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x00c))
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#define IIS1CONFIG (*(volatile unsigned long *)(MBAR2 + 0x010))
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@ -177,9 +190,11 @@
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#define U2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0d8))
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#define Q2CHANNELRECEIVE (*(volatile unsigned long *)(MBAR2 + 0x0dc))
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#define GPIO1_READ (*(volatile unsigned long *)(MBAR2 + 0x0b0))
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#define GPIO1_OUT (*(volatile unsigned long *)(MBAR2 + 0x0b4))
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#define GPIO1_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x0b8))
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#define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac))
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#define GPIO1_READ (*(volatile unsigned long *)(MBAR2 + 0x0b0))
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#define GPIO1_OUT (*(volatile unsigned long *)(MBAR2 + 0x0b4))
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#define GPIO1_ENABLE (*(volatile unsigned long *)(MBAR2 + 0x0b8))
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#define GPIO1_FUNCTION (*(volatile unsigned long *)(MBAR2 + 0x0bc))
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#define GPIO_INT_STAT (*(volatile unsigned long *)(MBAR2 + 0x0c0))
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#define GPIO_INT_CLEAR (*(volatile unsigned long *)(MBAR2 + 0x0c0))
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@ -222,8 +237,6 @@
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#define FLASHMEDIAINTSTAT (*(volatile unsigned long *)(MBAR2 + 0x47c))
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#define FLASHMEDIAINTCLEAR (*(volatile unsigned long *)(MBAR2 + 0x47c))
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#define DEVICE_ID (*(volatile unsigned long *)(MBAR2 + 0x0ac))
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/* DMA Registers ... */
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#define O_SAR 0x00 /* Source Address */
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@ -233,7 +233,7 @@ void tick_start(unsigned int interval_in_ms)
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TER0 = 0xff; /* Clear all events */
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ICR0 = (ICR0 & 0xff00ffff) | 0x008c0000; /* Interrupt on level 3.0 */
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ICR1 = 0x8c; /* Interrupt on level 3.0 */
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IMR &= ~0x200;
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}
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@ -286,8 +286,8 @@ void pcm_init(void)
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pcm_playing = false;
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pcm_paused = false;
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BUSMASTER_CTRL = 0x81; /* PARK[1,0]=10 + BCR24BIT */
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */
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DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
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DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1;
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DMACONFIG = 1; /* DMA0Req = PDOR3 */
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@ -295,7 +295,7 @@ void pcm_init(void)
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IIS2CONFIG = IIS_RESET;
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/* Enable interrupt at level 7, priority 0 */
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ICR4 = (ICR4 & 0xffff00ff) | 0x00001c00;
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ICR6 = 0x1c;
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IMR &= ~(1<<14); /* bit 14 is DMA0 */
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pcm_set_frequency(44100);
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@ -570,7 +570,7 @@ static void pcmrec_open(void)
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DIVR1 = 55; /* DMA1 is mapped into vector 55 in system.c */
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DMACONFIG = 1; /* DMA0Req = PDOR3, DMA1Req = PDIR2 */
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DMAROUTE = (DMAROUTE & 0xffff00ff) | DMA1_REQ_AUDIO_2;
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ICR4 = (ICR4 & 0xffffff00) | 0x0000001c; /* Enable interrupt at level 7, priority 0 */
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ICR7 = 0x1c; /* Enable interrupt at level 7, priority 0 */
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IMR &= ~(1<<15); /* bit 15 is DMA1 */
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init_done = 1;
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@ -585,8 +585,8 @@ static void pcmrec_close(void)
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#endif
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DMAROUTE = (DMAROUTE & 0xffff00ff);
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ICR4 = (ICR4 & 0xffffff00); /* Disable interrupt */
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IMR |= (1<<15); /* bit 15 is DMA1 */
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ICR7 = 0x00; /* Disable interrupt */
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IMR |= (1<<15); /* bit 15 is DMA1 */
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}
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@ -174,8 +174,7 @@ bool timer_register(int reg_prio, void (*unregister_callback)(void),
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IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */
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or_b(0x10, &TSTR); /* start timer 4 */
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#elif defined CPU_COLDFIRE
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/* ICR2 (Timer1) */
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ICR0 = (ICR0 & 0xffff00ff) | 0x00009000; /* interrupt on level 4.0 */
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ICR2 = 0x90; /* interrupt on level 4.0 */
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and_l(~(1<<10), &IMR);
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TMR1 |= 1; /* start timer */
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#endif
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