2005-03-18 11:39:28 +00:00
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/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 by Linus Nielsen Feltzing
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "config.h"
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#include "debug.h"
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#include "panic.h"
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#include <kernel.h>
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#ifndef SIMULATOR
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#include "cpu.h"
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#include "i2c.h"
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2005-08-06 10:12:19 +00:00
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#if defined(HAVE_UDA1380)
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2005-03-18 11:39:28 +00:00
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#include "uda1380.h"
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2005-12-16 11:00:44 +00:00
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#elif defined(HAVE_WM8975)
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#include "wm8975.h"
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2005-08-06 10:12:19 +00:00
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#elif defined(HAVE_TLV320)
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#include "tlv320.h"
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#endif
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2005-03-18 11:39:28 +00:00
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#include "system.h"
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#endif
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2005-06-19 18:41:53 +00:00
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#include "logf.h"
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2005-03-18 11:39:28 +00:00
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#include <stdio.h>
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#include <string.h>
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#include <stdarg.h>
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2005-06-05 23:05:10 +00:00
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#include "pcm_playback.h"
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2005-03-18 11:39:28 +00:00
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#include "lcd.h"
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#include "button.h"
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#include "file.h"
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#include "buffer.h"
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2005-03-28 00:00:24 +00:00
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#include "sprintf.h"
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#include "button.h"
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#include <string.h>
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2005-06-18 22:23:54 +00:00
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#ifdef HAVE_UDA1380
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-08-21 17:34:56 +00:00
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#define EBU_DEFPARM ((7 << 12) | (3 << 8) | (1 << 5) | (5 << 2))
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2005-11-27 01:11:25 +00:00
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#endif
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2005-08-21 17:34:56 +00:00
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#define IIS_DEFPARM(freq) ((freq << 12) | 0x300 | 4 << 2)
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#define IIS_RESET 0x800
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2005-03-28 00:00:24 +00:00
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static bool pcm_playing;
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2005-03-31 06:49:10 +00:00
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static bool pcm_paused;
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static int pcm_freq = 0x6; /* 44.1 is default */
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2005-03-18 11:39:28 +00:00
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2005-06-05 23:05:10 +00:00
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static unsigned char *next_start;
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static long next_size;
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2005-03-18 11:39:28 +00:00
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/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
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2005-03-31 06:49:10 +00:00
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static void dma_start(const void *addr, long size)
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{
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pcm_playing = true;
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2005-03-18 11:39:28 +00:00
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2005-03-31 06:49:10 +00:00
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addr = (void *)((unsigned long)addr & ~3); /* Align data */
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size &= ~3; /* Size must be multiple of 4 */
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2005-03-18 11:39:28 +00:00
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2005-03-31 06:49:10 +00:00
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/* Reset the audio FIFO */
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-12-27 18:00:45 +00:00
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EBU1CONFIG = IIS_RESET | EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-07-01 17:05:09 +00:00
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2005-03-18 11:39:28 +00:00
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/* Set up DMA transfer */
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2005-03-31 06:49:10 +00:00
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SAR0 = ((unsigned long)addr); /* Source address */
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DAR0 = (unsigned long)&PDOR3; /* Destination address */
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BCR0 = size; /* Bytes to transfer */
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2005-03-18 11:39:28 +00:00
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2005-03-31 06:49:10 +00:00
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/* Enable the FIFO and force one write to it */
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_DEFPARM(pcm_freq);
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2005-07-01 07:55:19 +00:00
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/* Also send the audio to S/PDIF */
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-08-21 17:34:56 +00:00
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EBU1CONFIG = EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-03-31 06:49:10 +00:00
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DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START;
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2005-03-18 11:39:28 +00:00
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}
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2005-06-10 10:58:45 +00:00
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/* Stops the DMA transfer and interrupt */
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static void dma_stop(void)
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{
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pcm_playing = false;
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2005-06-30 20:02:56 +00:00
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DCR0 = 0;
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2005-12-06 09:09:21 +00:00
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DSR0 = 1;
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2005-06-10 10:58:45 +00:00
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/* Reset the FIFO */
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-12-27 18:00:45 +00:00
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EBU1CONFIG = IIS_RESET | EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-07-07 07:15:05 +00:00
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2005-07-01 17:05:09 +00:00
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next_start = NULL;
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next_size = 0;
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pcm_paused = false;
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2005-06-10 10:58:45 +00:00
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}
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2005-07-25 05:50:47 +00:00
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/*
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* This function goes directly into the DMA buffer to calculate the left and
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2005-08-29 20:07:17 +00:00
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* right peak values. To avoid missing peaks it tries to look forward two full
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* peek periods (2/HZ sec, 100% overlap), although it's always possible that
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* the entire period will not be visible. To reduce CPU load it only looks at
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* every third sample, and this can be reduced even further if needed (even
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* every tenth sample would still be pretty accurate).
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2005-07-25 05:50:47 +00:00
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*/
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2005-08-29 20:07:17 +00:00
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#define PEAK_SAMPLES (44100*2/HZ) /* 44100 samples * 2 / 100 Hz tick */
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#define PEAK_STRIDE 3 /* every 3rd sample is plenty... */
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2005-07-25 05:50:47 +00:00
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void pcm_calculate_peaks(int *left, int *right)
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2005-07-17 19:29:02 +00:00
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{
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2005-07-25 05:50:47 +00:00
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long samples = (BCR0 & 0xffffff) / 4;
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short *addr = (short *) (SAR0 & ~3);
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if (samples > PEAK_SAMPLES)
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samples = PEAK_SAMPLES;
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samples /= PEAK_STRIDE;
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if (left && right) {
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int left_peak = 0, right_peak = 0, value;
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while (samples--) {
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if ((value = addr [0]) > left_peak)
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left_peak = value;
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else if (-value > left_peak)
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left_peak = -value;
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2005-07-17 19:29:02 +00:00
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2005-07-25 05:50:47 +00:00
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if ((value = addr [PEAK_STRIDE | 1]) > right_peak)
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right_peak = value;
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else if (-value > right_peak)
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right_peak = -value;
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addr += PEAK_STRIDE * 2;
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2005-07-17 19:29:02 +00:00
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}
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2005-07-25 05:50:47 +00:00
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*left = left_peak;
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*right = right_peak;
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2005-07-17 19:29:02 +00:00
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}
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2005-07-25 05:50:47 +00:00
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else if (left || right) {
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int peak_value = 0, value;
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2005-07-17 19:29:02 +00:00
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2005-07-25 05:50:47 +00:00
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if (right)
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addr += (PEAK_STRIDE | 1);
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2005-07-17 19:29:02 +00:00
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2005-07-25 05:50:47 +00:00
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while (samples--) {
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if ((value = addr [0]) > peak_value)
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peak_value = value;
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else if (-value > peak_value)
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peak_value = -value;
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addr += PEAK_STRIDE * 2;
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}
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if (left)
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*left = peak_value;
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else
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*right = peak_value;
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}
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2005-07-17 19:29:02 +00:00
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}
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2005-03-28 00:00:24 +00:00
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/* sets frequency of input to DAC */
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void pcm_set_frequency(unsigned int frequency)
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{
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2005-03-31 06:49:10 +00:00
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switch(frequency)
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{
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2005-03-28 00:00:24 +00:00
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case 11025:
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pcm_freq = 0x4;
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2005-07-01 07:55:19 +00:00
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uda1380_set_nsorder(3);
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2005-03-28 00:00:24 +00:00
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break;
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2005-07-01 07:55:19 +00:00
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case 22050:
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2005-03-28 00:00:24 +00:00
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pcm_freq = 0x6;
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2005-07-01 07:55:19 +00:00
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uda1380_set_nsorder(3);
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2005-03-28 00:00:24 +00:00
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break;
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2005-07-01 07:55:19 +00:00
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case 44100:
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2005-03-28 00:00:24 +00:00
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default:
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2005-07-01 07:55:19 +00:00
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pcm_freq = 0xC;
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uda1380_set_nsorder(5);
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2005-03-31 06:49:10 +00:00
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break;
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}
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2005-03-28 00:00:24 +00:00
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}
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2005-03-18 11:39:28 +00:00
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/* the registered callback function to ask for more mp3 data */
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static void (*callback_for_more)(unsigned char**, long*) = NULL;
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2005-07-13 12:48:22 +00:00
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void pcm_play_data(void (*get_more)(unsigned char** start, long* size))
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2005-06-05 23:05:10 +00:00
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{
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2005-07-13 12:48:22 +00:00
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unsigned char *start;
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long size;
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2005-08-06 10:12:19 +00:00
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2005-03-18 11:39:28 +00:00
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callback_for_more = get_more;
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2005-08-06 10:12:19 +00:00
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2005-07-13 12:48:22 +00:00
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get_more((unsigned char **)&start, (long *)&size);
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2005-06-07 06:34:54 +00:00
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get_more(&next_start, &next_size);
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2005-07-01 17:05:09 +00:00
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dma_start(start, size);
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2005-03-18 11:39:28 +00:00
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}
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2005-07-22 06:32:55 +00:00
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long pcm_get_bytes_waiting(void)
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{
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return next_size + (BCR0 & 0xffffff);
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}
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2005-03-18 11:39:28 +00:00
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void pcm_play_stop(void)
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{
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2005-06-14 09:25:28 +00:00
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if (pcm_playing) {
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2005-06-14 07:54:09 +00:00
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dma_stop();
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2005-06-14 09:25:28 +00:00
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}
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2005-03-18 11:39:28 +00:00
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}
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2005-03-31 06:49:10 +00:00
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void pcm_play_pause(bool play)
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{
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2005-07-13 12:48:22 +00:00
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if(pcm_paused && play && next_size)
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2005-03-31 06:49:10 +00:00
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{
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2005-06-30 20:02:56 +00:00
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logf("unpause");
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/* Reset chunk size so dma has enough data to fill the fifo. */
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2005-07-01 17:13:33 +00:00
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/* This shouldn't be needed anymore. */
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//SAR0 = (unsigned long)next_start;
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//BCR0 = next_size;
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2005-03-31 06:49:10 +00:00
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/* Enable the FIFO and force one write to it */
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_DEFPARM(pcm_freq);
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-08-21 17:34:56 +00:00
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EBU1CONFIG = EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-06-30 20:02:56 +00:00
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DCR0 |= DMA_EEXT | DMA_START;
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2005-03-31 06:49:10 +00:00
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}
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else if(!pcm_paused && !play)
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{
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2005-06-30 20:02:56 +00:00
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logf("pause");
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2005-08-06 10:12:19 +00:00
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2005-06-30 20:02:56 +00:00
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/* Disable DMA peripheral request. */
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DCR0 &= ~DMA_EEXT;
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2005-08-21 17:34:56 +00:00
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IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
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2005-11-27 01:11:25 +00:00
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#ifdef HAVE_SPDIF_OUT
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2005-12-27 18:00:45 +00:00
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EBU1CONFIG = IIS_RESET | EBU_DEFPARM;
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2005-11-27 01:11:25 +00:00
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#endif
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2005-03-31 06:49:10 +00:00
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}
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2005-06-10 20:46:39 +00:00
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pcm_paused = !play;
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2005-03-31 06:49:10 +00:00
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}
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2005-07-13 12:48:22 +00:00
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bool pcm_is_paused(void)
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{
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return pcm_paused;
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}
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2005-03-18 11:39:28 +00:00
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bool pcm_is_playing(void)
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{
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return pcm_playing;
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}
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/* DMA0 Interrupt is called when the DMA has finished transfering a chunk */
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void DMA0(void) __attribute__ ((interrupt_handler, section(".icode")));
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void DMA0(void)
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{
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2005-03-28 00:00:24 +00:00
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int res = DSR0;
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2005-03-18 11:39:28 +00:00
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DSR0 = 1; /* Clear interrupt */
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2005-07-01 17:05:09 +00:00
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DCR0 &= ~DMA_EEXT;
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2005-08-06 10:12:19 +00:00
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2005-03-31 06:49:10 +00:00
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/* Stop on error */
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if(res & 0x70)
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2005-03-28 00:00:24 +00:00
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{
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2005-07-22 16:46:27 +00:00
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pcm_play_stop();
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2005-07-07 07:15:05 +00:00
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logf("DMA Error:0x%04x", res);
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2005-03-28 00:00:24 +00:00
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}
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2005-03-18 11:39:28 +00:00
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else
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{
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2005-06-05 23:05:10 +00:00
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if(next_size)
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2005-03-31 06:49:10 +00:00
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{
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2005-06-05 23:05:10 +00:00
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SAR0 = (unsigned long)next_start; /* Source address */
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BCR0 = next_size; /* Bytes to transfer */
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2005-07-01 17:05:09 +00:00
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DCR0 |= DMA_EEXT;
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2005-06-07 06:34:54 +00:00
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if (callback_for_more)
|
2005-06-05 23:05:10 +00:00
|
|
|
callback_for_more(&next_start, &next_size);
|
2005-03-31 06:49:10 +00:00
|
|
|
}
|
|
|
|
else
|
|
|
|
{
|
|
|
|
/* Finished playing */
|
2005-07-22 16:46:27 +00:00
|
|
|
pcm_play_stop();
|
2005-07-07 07:15:05 +00:00
|
|
|
logf("DMA No Data:0x%04x", res);
|
2005-03-31 06:49:10 +00:00
|
|
|
}
|
2005-03-18 11:39:28 +00:00
|
|
|
}
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-03-18 11:39:28 +00:00
|
|
|
IPR |= (1<<14); /* Clear pending interrupt request */
|
|
|
|
}
|
2005-03-31 06:49:10 +00:00
|
|
|
|
|
|
|
void pcm_init(void)
|
|
|
|
{
|
|
|
|
pcm_playing = false;
|
|
|
|
pcm_paused = false;
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-11-05 03:28:20 +00:00
|
|
|
MPARK = 0x81; /* PARK[1,0]=10 + BCR24BIT */
|
|
|
|
DIVR0 = 54; /* DMA0 is mapped into vector 54 in system.c */
|
2005-03-31 06:49:10 +00:00
|
|
|
DMAROUTE = (DMAROUTE & 0xffffff00) | DMA0_REQ_AUDIO_1;
|
|
|
|
DMACONFIG = 1; /* DMA0Req = PDOR3 */
|
|
|
|
|
|
|
|
/* Reset the audio FIFO */
|
2005-08-21 17:34:56 +00:00
|
|
|
IIS2CONFIG = IIS_RESET;
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-03-31 06:49:10 +00:00
|
|
|
/* Enable interrupt at level 7, priority 0 */
|
2005-11-05 03:28:20 +00:00
|
|
|
ICR6 = 0x1c;
|
2005-03-31 06:49:10 +00:00
|
|
|
IMR &= ~(1<<14); /* bit 14 is DMA0 */
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-03-31 06:49:10 +00:00
|
|
|
pcm_set_frequency(44100);
|
2005-08-06 10:12:19 +00:00
|
|
|
|
2005-08-21 17:34:56 +00:00
|
|
|
/* Prevent pops (resets DAC to zero point) */
|
|
|
|
IIS2CONFIG = IIS_DEFPARM(pcm_freq) | IIS_RESET;
|
|
|
|
|
2005-08-06 10:12:19 +00:00
|
|
|
#if defined(HAVE_UDA1380)
|
2005-08-21 17:34:56 +00:00
|
|
|
/* Initialize default register values. */
|
|
|
|
uda1380_init();
|
|
|
|
|
2005-08-28 15:33:37 +00:00
|
|
|
/* Sleep a while so the power can stabilize (especially a long
|
|
|
|
delay is needed for the line out connector). */
|
|
|
|
sleep(HZ);
|
2005-08-21 17:34:56 +00:00
|
|
|
|
2005-08-28 15:33:37 +00:00
|
|
|
/* Power on FSDAC and HP amp. */
|
|
|
|
uda1380_enable_output(true);
|
2005-08-21 17:34:56 +00:00
|
|
|
|
|
|
|
/* Unmute the master channel (DAC should be at zero point now). */
|
|
|
|
uda1380_mute(false);
|
2005-08-28 15:33:37 +00:00
|
|
|
|
2005-08-06 10:12:19 +00:00
|
|
|
#elif defined(HAVE_TLV320)
|
2005-08-21 17:34:56 +00:00
|
|
|
tlv320_init();
|
2005-08-06 10:12:19 +00:00
|
|
|
tlv320_enable_output(true);
|
2005-08-21 17:34:56 +00:00
|
|
|
sleep(HZ/4);
|
|
|
|
tlv320_mute(false);
|
2005-08-06 10:12:19 +00:00
|
|
|
#endif
|
2005-08-21 17:34:56 +00:00
|
|
|
|
|
|
|
|
2005-07-07 07:15:05 +00:00
|
|
|
/* Call dma_stop to initialize everything. */
|
|
|
|
dma_stop();
|
2005-04-14 11:51:31 +00:00
|
|
|
}
|
2005-06-18 22:23:54 +00:00
|
|
|
|
2005-11-12 15:29:43 +00:00
|
|
|
#elif defined(HAVE_WM8975)
|
|
|
|
|
2005-12-16 11:00:44 +00:00
|
|
|
/* We need to unify this code with the uda1380 code as much as possible, but
|
|
|
|
we will keep it separate during early development.
|
2005-11-12 15:29:43 +00:00
|
|
|
*/
|
|
|
|
|
2005-12-16 11:00:44 +00:00
|
|
|
static bool pcm_playing;
|
|
|
|
static bool pcm_paused;
|
|
|
|
static int pcm_freq = 0x6; /* 44.1 is default */
|
|
|
|
|
|
|
|
static unsigned char *next_start;
|
|
|
|
static long next_size;
|
|
|
|
|
|
|
|
/* Set up the DMA transfer that kicks in when the audio FIFO gets empty */
|
|
|
|
static void dma_start(const void *addr, long size)
|
|
|
|
{
|
|
|
|
pcm_playing = true;
|
|
|
|
|
|
|
|
addr = (void *)((unsigned long)addr & ~3); /* Align data */
|
|
|
|
size &= ~3; /* Size must be multiple of 4 */
|
|
|
|
|
2005-12-16 11:42:39 +00:00
|
|
|
/* Disable playback for now */
|
|
|
|
pcm_playing = false;
|
2005-12-16 11:00:44 +00:00
|
|
|
return;
|
|
|
|
|
|
|
|
/* This is the uda1380 code */
|
|
|
|
#if 0
|
|
|
|
/* Reset the audio FIFO */
|
|
|
|
|
|
|
|
/* Set up DMA transfer */
|
|
|
|
SAR0 = ((unsigned long)addr); /* Source address */
|
|
|
|
DAR0 = (unsigned long)&PDOR3; /* Destination address */
|
|
|
|
BCR0 = size; /* Bytes to transfer */
|
|
|
|
|
|
|
|
/* Enable the FIFO and force one write to it */
|
|
|
|
IIS2CONFIG = IIS_DEFPARM(pcm_freq);
|
|
|
|
|
|
|
|
DCR0 = DMA_INT | DMA_EEXT | DMA_CS | DMA_SINC | DMA_START;
|
|
|
|
#endif
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Stops the DMA transfer and interrupt */
|
|
|
|
static void dma_stop(void)
|
|
|
|
{
|
|
|
|
pcm_playing = false;
|
|
|
|
|
|
|
|
#if 0
|
|
|
|
/* This is the uda1380 code */
|
|
|
|
DCR0 = 0;
|
|
|
|
DSR0 = 1;
|
|
|
|
/* Reset the FIFO */
|
|
|
|
IIS2CONFIG = IIS_RESET | IIS_DEFPARM(pcm_freq);
|
|
|
|
#endif
|
|
|
|
next_start = NULL;
|
|
|
|
next_size = 0;
|
|
|
|
pcm_paused = false;
|
|
|
|
}
|
|
|
|
|
|
|
|
|
2005-11-12 15:29:43 +00:00
|
|
|
void pcm_init(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
pcm_playing = false;
|
|
|
|
pcm_paused = false;
|
|
|
|
|
|
|
|
/* Initialize default register values. */
|
|
|
|
wm8975_init();
|
|
|
|
|
|
|
|
/* The uda1380 needs a sleep(HZ) here - do we need one? */
|
2005-11-12 15:29:43 +00:00
|
|
|
|
2005-12-16 11:00:44 +00:00
|
|
|
/* Power on */
|
|
|
|
wm8975_enable_output(true);
|
|
|
|
|
|
|
|
/* Unmute the master channel (DAC should be at zero point now). */
|
|
|
|
wm8975_mute(false);
|
|
|
|
|
|
|
|
/* Call dma_stop to initialize everything. */
|
|
|
|
dma_stop();
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_set_frequency(unsigned int frequency)
|
|
|
|
{
|
|
|
|
(void)frequency;
|
2005-12-16 11:00:44 +00:00
|
|
|
pcm_freq=frequency;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
2005-12-16 11:00:44 +00:00
|
|
|
/* the registered callback function to ask for more mp3 data */
|
|
|
|
static void (*callback_for_more)(unsigned char**, long*) = NULL;
|
|
|
|
|
2005-11-12 15:29:43 +00:00
|
|
|
void pcm_play_data(void (*get_more)(unsigned char** start, long* size))
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
unsigned char *start;
|
|
|
|
long size;
|
|
|
|
|
|
|
|
callback_for_more = get_more;
|
|
|
|
|
|
|
|
get_more((unsigned char **)&start, (long *)&size);
|
|
|
|
get_more(&next_start, &next_size);
|
|
|
|
|
|
|
|
dma_start(start, size);
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_stop(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
if (pcm_playing) {
|
|
|
|
dma_stop();
|
|
|
|
}
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_pause(bool play)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
if(pcm_paused && play && next_size)
|
|
|
|
{
|
|
|
|
logf("unpause");
|
|
|
|
/* We need to enable DMA here */
|
|
|
|
}
|
|
|
|
else if(!pcm_paused && !play)
|
|
|
|
{
|
|
|
|
logf("pause");
|
|
|
|
/* We need to disable DMA here */
|
|
|
|
}
|
|
|
|
pcm_paused = !play;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_paused(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
return pcm_paused;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_playing(void)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
return pcm_playing;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_calculate_peaks(int *left, int *right)
|
|
|
|
{
|
2005-12-16 11:00:44 +00:00
|
|
|
*left=0;
|
|
|
|
*right=0;
|
2005-11-12 15:29:43 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
long pcm_get_bytes_waiting(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2006-01-12 00:35:50 +00:00
|
|
|
#elif CONFIG_CPU == PNX0101
|
|
|
|
|
|
|
|
/* TODO: Implement for iFP7xx
|
|
|
|
For now, just implement some dummy functions.
|
|
|
|
*/
|
|
|
|
|
|
|
|
void pcm_init(void)
|
|
|
|
{
|
|
|
|
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_set_frequency(unsigned int frequency)
|
|
|
|
{
|
|
|
|
(void)frequency;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_data(void (*get_more)(unsigned char** start, long* size))
|
|
|
|
{
|
|
|
|
(void)get_more;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_stop(void)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_play_pause(bool play)
|
|
|
|
{
|
|
|
|
(void)play;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_paused(void)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
bool pcm_is_playing(void)
|
|
|
|
{
|
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
|
|
|
void pcm_calculate_peaks(int *left, int *right)
|
|
|
|
{
|
|
|
|
(void)left;
|
|
|
|
(void)right;
|
|
|
|
}
|
|
|
|
|
|
|
|
long pcm_get_bytes_waiting(void)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2005-11-12 15:29:43 +00:00
|
|
|
#endif
|