rockbox/firmware/target/mips
Aidan MacDonald e85bc74b30 x1000: GPIO refactor
The GPIO API was pretty clunky and pin settings were decentralized,
making it hard to see what was happening and making GPIO stuff look
like a mess, frankly.

Instead of passing clunky (port, pin) pairs everywhere, GPIOs are now
identified with a single int. The extra overhead should be minimal as
GPIO configuration is generally not on a performance-critical path.

Pin assignments are now mostly consolidated in gpio-target.h and put
in various tables so gpio_init() can assign most pins at boot time.

Most drivers no longer need to touch GPIOs and basic pin I/O stuff
can happen without config since pins are put into the right state.
IRQ pins still need to be configured manually before use.

Change-Id: Ic5326284b0b2a2f613e9e76a41cb50e24af3aa47
2021-06-06 11:06:14 +00:00
..
ingenic_jz47xx MIPS: remove .MIPS.abiflags section 2021-04-26 12:41:06 +00:00
ingenic_x1000 x1000: GPIO refactor 2021-06-06 11:06:14 +00:00
mipsr2-endian.h MIPS: add another mipsr2 endian function 2021-05-29 15:35:50 +00:00
mmu-mips.c New port: FiiO M3K on bare metal 2021-03-28 00:01:37 +00:00
mmu-mips.h MIPS: emulate -ffunction-sections with macros in mmu-mips 2021-04-25 14:04:38 +00:00