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MIPS: emulate -ffunction-sections with macros in mmu-mips

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Using a macro to put each function in its own .icode-based section
allows us to put the functions in IRAM _and_ have linker GC. This
removes a troublesome #ifdef BOOTLOADER_SPL on the X1000 target.

Change-Id: Ia7b59778f5c36b7970dee4280547e434a1f4fc5a
This commit is contained in:
Aidan MacDonald 2021-04-25 13:43:58 +01:00
parent c37555d30d
commit d6220f618b
6 changed files with 12 additions and 21 deletions
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2
firmware/target/mips/ingenic_jz47xx/app.lds
View file

@ -66,7 +66,7 @@ SECTIONS
KEEP(*(.vectors.4));
KEEP(*(.vectors));
*(.icode);
*(.icode*);
*(.irodata);
*(.idata);
KEEP(*(.vectors))

2
firmware/target/mips/ingenic_jz47xx/boot.lds
View file

@ -58,7 +58,7 @@ SECTIONS
KEEP(*(.vectors.4));
KEEP(*(.vectors));
*(.icode);
*(.icode*);
*(.irodata);
*(.idata);
KEEP(*(.vectors*))

2
firmware/target/mips/ingenic_x1000/app.lds
View file

@ -63,7 +63,7 @@ SECTIONS
KEEP(*(.vectors.4));
KEEP(*(.vectors));
*(.icode);
*(.icode*);
*(.irodata);
*(.idata);
_iramend = .;

1
firmware/target/mips/ingenic_x1000/spl.lds
View file

@ -26,6 +26,7 @@ SECTIONS
{
*(.init.text);
*(.text*);
*(.icode*);
} > TCSM
. = ALIGN(4);

9
firmware/target/mips/ingenic_x1000/system-target.h
View file

@ -28,15 +28,6 @@
#define CACHEALIGN_BITS 5
#define CACHE_SIZE (16*1024)
#ifdef BOOTLOADER_SPL
/* This saves ~200 bytes in the SPL by allowing -ffunction-sections to split
* up the cache management functions, most of which aren't called by the SPL.
* If they are placed in .icode, then they all end up in one section and the
* linker can't discard the unused functions.
*/
# define MIPS_CACHEFUNC_ATTR
#endif
#ifdef DEBUG
/* Define this to get CPU idle stats, visible in the debug menu. */
# define X1000_CPUIDLE_STATS

17
firmware/target/mips/mmu-mips.h
View file

@ -28,33 +28,32 @@
* called safely eg. by the bootloader or RoLo, which need to flush the
* cache before jumping to the loaded binary.
*/
#ifndef MIPS_CACHEFUNC_ATTR
# define MIPS_CACHEFUNC_ATTR __attribute__((section(".icode")))
#endif
#define MIPS_CACHEFUNC_API(ret, name, args) \
ret name args __attribute__((section( ".icode." #name )))
void map_address(unsigned long virtual, unsigned long physical,
unsigned long length, unsigned int cache_flags);
void mmu_init(void);
/* Commits entire DCache */
void commit_dcache(void) MIPS_CACHEFUNC_ATTR;
MIPS_CACHEFUNC_API(void, commit_dcache, (void));
/* Commit and discard entire DCache, will do writeback */
void commit_discard_dcache(void) MIPS_CACHEFUNC_ATTR;
MIPS_CACHEFUNC_API(void, commit_discard_dcache, (void));
/* Write DCache back to RAM for the given range and remove cache lines
* from DCache afterwards */
void commit_discard_dcache_range(const void *base, unsigned int size) MIPS_CACHEFUNC_ATTR;
MIPS_CACHEFUNC_API(void, commit_discard_dcache_range, (const void *base, unsigned int size));
/* Write DCache back to RAM for the given range */
void commit_dcache_range(const void *base, unsigned int size) MIPS_CACHEFUNC_ATTR;
MIPS_CACHEFUNC_API(void, commit_dcache_range, (const void *base, unsigned int size));
/*
* Remove cache lines for the given range from DCache
* will *NOT* do write back except for buffer edges not on a line boundary
*/
void discard_dcache_range(const void *base, unsigned int size) MIPS_CACHEFUNC_ATTR;
MIPS_CACHEFUNC_API(void, discard_dcache_range, (const void *base, unsigned int size));
/* Discards the entire ICache, and commit+discards the entire DCache */
void commit_discard_idcache(void) MIPS_CACHEFUNC_ATTR;
MIPS_CACHEFUNC_API(void, commit_discard_idcache, (void));
#endif /* __MMU_MIPS_INCLUDE_H */