541 lines
17 KiB
C
541 lines
17 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2007 by Rob Purchase
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "kernel.h"
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#include "system.h"
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#include "panic.h"
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#include "ascodec.h"
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#include "adc.h"
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#include "dma-target.h"
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#include "clock-target.h"
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#include "fmradio_i2c.h"
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#include "button.h"
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#include "backlight-target.h"
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#include "lcd.h"
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struct mutex cpufreq_mtx;
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/* Charge Pump and Power management Settings */
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#define AS314_CP_DCDC3_SETTING \
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((0<<7) | /* CP_SW Auto-Switch Margin 0=200/300 1=150/255 */ \
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(0<<6) | /* CP_on 0=Normal op 1=Chg Pump Always On */ \
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(0<<5) | /* LREG_CPnot Always write 0 */ \
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(0<<3) | /* DCDC3p BVDD setting 3.6/3.2/3.1/3.0 */ \
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(1<<2) | /* LREG_off 1=Auto mode switching 0=Length Reg only*/\
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(0<<0) ) /* CVDDp Core Voltage Setting 1.2/1.15/1.10/1.05*/
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#define CVDD_1_20 0
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#define CVDD_1_15 1
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#define CVDD_1_10 2
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#define CVDD_1_05 3
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#define default_interrupt(name) \
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extern __attribute__((weak,alias("UIRQ"))) void name (void)
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#if CONFIG_USBOTG != USBOTG_DESIGNWARE
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static void UIRQ (void) __attribute__((interrupt ("IRQ")));
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#endif
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void irq_handler(void) __attribute__((naked, interrupt ("IRQ")));
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void fiq_handler(void) __attribute__((interrupt ("FIQ")));
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default_interrupt(INT_WATCHDOG);
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default_interrupt(INT_TIMER1);
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default_interrupt(INT_TIMER2);
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default_interrupt(INT_USB_FUNC);
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default_interrupt(INT_DMAC);
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default_interrupt(INT_NAND);
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default_interrupt(INT_IDE);
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default_interrupt(INT_MCI0);
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default_interrupt(INT_MCI1);
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default_interrupt(INT_AUDIO);
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default_interrupt(INT_SSP);
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default_interrupt(INT_I2C_MS);
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default_interrupt(INT_I2C_AUDIO);
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default_interrupt(INT_I2SIN);
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default_interrupt(INT_I2SOUT);
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default_interrupt(INT_UART);
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default_interrupt(INT_GPIOD);
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default_interrupt(RESERVED1); /* Interrupt 17 : unused */
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default_interrupt(INT_CGU);
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default_interrupt(INT_MEMORY_STICK);
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default_interrupt(INT_DBOP);
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default_interrupt(RESERVED2); /* Interrupt 21 : unused */
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default_interrupt(RESERVED3); /* Interrupt 22 : unused */
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default_interrupt(RESERVED4); /* Interrupt 23 : unused */
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default_interrupt(RESERVED5); /* Interrupt 24 : unused */
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default_interrupt(RESERVED6); /* Interrupt 25 : unused */
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default_interrupt(RESERVED7); /* Interrupt 26 : unused */
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default_interrupt(RESERVED8); /* Interrupt 27 : unused */
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default_interrupt(RESERVED9); /* Interrupt 28 : unused */
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/* INT_GPIOA is declared in this file */
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void INT_GPIOA(void);
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default_interrupt(INT_GPIOB);
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default_interrupt(INT_GPIOC);
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static const char const irqname[][9] =
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{
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"WATCHDOG", "TIMER1", "TIMER2", "USB", "DMAC", "NAND",
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"IDE", "MCI0", "MCI1", "AUDIO", "SSP", "I2C_MS",
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"I2C_AUDIO", "I2SIN", "I2SOUT", "UART", "GPIOD", "RESERVD1",
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"CGU", "MS", "DBOP", "RESERVD2", "RESERVD3", "RESERVD4",
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"RESERVD5", "RESERVD6", "RESERVD7", "RESERVD8", "RESERVD9", "GPIOA",
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"GPIOB", "GPIOC"
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};
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static void UIRQ(void)
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{
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bool masked = false;
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int status = VIC_IRQ_STATUS;
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if(status == 0)
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{
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status = VIC_RAW_INTR; /* masked interrupts */
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#if CONFIG_USBOTG == USBOTG_DESIGNWARE
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/* spurious interrupts from USB are expected */
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if (status & INTERRUPT_USB)
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return;
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#endif
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masked = true;
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}
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if(status == 0)
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panicf("Unhandled IRQ (source unknown!)");
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unsigned irq_no = 31 - __builtin_clz(status);
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panicf("Unhandled %smasked IRQ %02X: %s (status 0x%8X)",
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masked ? "" : "un", irq_no, irqname[irq_no], status);
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}
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/* Vectored interrupts (16 available) */
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static const struct { int source; void (*isr) (void); } vec_int_srcs[] =
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{
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/* Highest priority at the top of the list */
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#if defined(HAVE_HOTSWAP) || defined(HAVE_RDS_CAP) || \
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(defined(SANSA_FUZEV2) && !INCREASED_SCROLLWHEEL_POLLING)
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/* If GPIOA ISR is interrupted, things seem to go wonky ?? */
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{ INT_SRC_GPIOA, INT_GPIOA },
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#endif
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#ifdef HAVE_RECORDING
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{ INT_SRC_I2SIN, INT_I2SIN }, /* For recording */
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#endif
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{ INT_SRC_DMAC, INT_DMAC }, /* Playback follows recording */
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{ INT_SRC_NAND, INT_NAND },
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#if (defined HAVE_MULTIDRIVE && CONFIG_CPU == AS3525)
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{ INT_SRC_MCI0, INT_MCI0 },
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#endif
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{ INT_SRC_USB, INT_USB_FUNC, },
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{ INT_SRC_TIMER1, INT_TIMER1 },
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{ INT_SRC_TIMER2, INT_TIMER2 },
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{ INT_SRC_I2C_AUDIO, INT_I2C_AUDIO },
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{ INT_SRC_AUDIO, INT_AUDIO },
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/* Lowest priority at the end of the list */
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};
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static void setup_vic(void)
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{
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CGU_PERI |= CGU_VIC_CLOCK_ENABLE; /* enable VIC */
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VIC_INT_EN_CLEAR = 0xffffffff; /* disable all interrupt lines */
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VIC_INT_SELECT = 0; /* only IRQ, no FIQ */
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*VIC_DEF_VECT_ADDR = UIRQ;
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for(unsigned int i = 0; i < ARRAYLEN(vec_int_srcs); i++)
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{
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VIC_VECT_ADDRS[i] = vec_int_srcs[i].isr;
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VIC_VECT_CNTLS[i] = (1<<5) | vec_int_srcs[i].source;
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}
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/* Reset priority hardware */
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for(unsigned int i = 0; i < 32; i++)
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*VIC_VECT_ADDR = 0;
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}
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void INT_GPIOA(void)
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{
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#ifdef HAVE_HOTSWAP
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void sd_gpioa_isr(void);
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sd_gpioa_isr();
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#endif
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#if defined(SANSA_FUZEV2) && !INCREASED_SCROLLWHEEL_POLLING
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void button_gpioa_isr(void);
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button_gpioa_isr();
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#endif
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#ifdef HAVE_RDS_CAP
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void tuner_isr(void);
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tuner_isr();
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#endif
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}
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void irq_handler(void)
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{
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/* Worst-case IRQ stack usage with 10 vectors:
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* 10*4*10 = 400 bytes (100 words)
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*
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* No SVC stack is used by pro/epi-logue code
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*/
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asm volatile (
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"sub lr, lr, #4 \n" /* Create return address */
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"stmfd sp!, { r0-r5, r12, lr } \n" /* Save what gets clobbered */
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"ldr r0, =0xc6010030 \n" /* Obtain VIC address (before SPSR read!) */
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"ldr r12, [r0] \n" /* Load Vector */
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"mrs r1, spsr \n" /* Save SPSR_irq */
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"stmfd sp!, { r0-r1 } \n" /* Must have something bet. mrs and msr */
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"msr cpsr_c, #0x13 \n" /* Switch to SVC mode, enable IRQ */
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"and r4, sp, #4 \n" /* Align SVC stack to 8 bytes, save */
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"sub sp, sp, r4 \n"
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"mov r5, lr \n" /* Save lr_SVC */
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#if ARM_ARCH >= 5
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"blx r12 \n" /* Call handler */
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#else
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"mov lr, pc \n"
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"bx r12 \n"
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#endif
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"add sp, sp, r4 \n" /* Undo alignment fudge */
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"mov lr, r5 \n" /* Restore lr_SVC */
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"msr cpsr_c, #0x92 \n" /* Mask IRQ, return to IRQ mode */
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"ldmfd sp!, { r0-r1 } \n" /* Pop VIC address, SPSR_irq */
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"str r0, [r0] \n" /* Ack end of ISR to VIC */
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"msr spsr_cxsf, r1 \n" /* Restore SPSR_irq */
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"ldmfd sp!, { r0-r5, r12, pc }^ \n" /* Restore regs, and RFE */
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);
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}
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void fiq_handler(void)
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{
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}
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#if defined(SANSA_C200V2)
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int c200v2_variant;
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static void check_model_variant(void)
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{
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unsigned int i;
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unsigned int saved_dir = GPIOA_DIR;
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/* Make A7 input */
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GPIOA_DIR &= ~(1<<7);
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/* wait a little to allow the pullup/pulldown resistor
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* to charge the input capacitance */
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for (i=0; i<1000; i++) asm volatile ("nop\n");
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/* read the pullup/pulldown value on A7 to determine the variant */
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c200v2_variant = !GPIOA_PIN(7);
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GPIOA_DIR = saved_dir;
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}
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#elif defined(SANSA_FUZEV2) || defined(SANSA_CLIPPLUS) || defined(SANSA_CLIPZIP)
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int amsv2_variant;
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static void check_model_variant(void)
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{
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GPIOB_DIR &= ~(1<<5);
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amsv2_variant = !!GPIOB_PIN(5);
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}
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#else
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static inline void check_model_variant(void)
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{
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}
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#endif /* model selection */
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void system_init(void)
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{
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#if CONFIG_CPU == AS3525v2
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CCU_SRC = 0x57D7BF0;
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#else
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CCU_SRC = 0x1fffff0
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& ~CCU_SRC_IDE_EN; /* FIXME */
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#endif
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unsigned int reset_loops = 640;
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while(reset_loops--)
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CCU_SRL = CCU_SRL_MAGIC_NUMBER;
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CCU_SRC = CCU_SRL = 0;
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CCU_SCON = 1; /* AHB master's priority configuration :
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TIC (Test Interface Controller) > DMA > USB > IDE > ARM */
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CGU_PROC = 0; /* fclk 24 MHz */
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#if CONFIG_CPU == AS3525v2
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/* pclk is always based on PLLA, since we don't know the current PLLA speed,
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* avoid having pclk too fast and hope it's not too low */
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CGU_PERI |= 0xf << 2; /* pclk lowest */
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#else
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CGU_PERI &= ~0x7f; /* pclk 24 MHz */
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#endif
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/* bits 31:30 should be set to 0 in arm926-ejs */
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asm volatile(
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"mrc p15, 0, r0, c1, c0 \n" /* control register */
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"bic r0, r0, #3<<30 \n" /* clears bus bits : sets fastbus */
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"mcr p15, 0, r0, c1, c0 \n"
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: : : "r0" );
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CGU_COUNTA = CGU_LOCK_CNT;
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CGU_PLLA = AS3525_PLLA_SETTING;
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CGU_PLLASUP = 0; /* enable PLLA */
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while(!(CGU_INTCTRL & CGU_PLLA_LOCK)); /* wait until PLLA is locked */
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#if AS3525_MCLK_SEL == AS3525_CLK_PLLB
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CGU_COUNTB = CGU_LOCK_CNT;
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CGU_PLLB = AS3525_PLLB_SETTING;
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CGU_PLLBSUP = 0; /* enable PLLB */
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while(!(CGU_INTCTRL & CGU_PLLB_LOCK)); /* wait until PLLB is locked */
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#endif
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/* Set FCLK frequency */
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CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
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(AS3525_FCLK_PREDIV << 2) |
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AS3525_FCLK_SEL);
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/* Set PCLK frequency */
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CGU_PERI = ((CGU_PERI & ~0x7F) | /* reset divider & clksel bits */
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(AS3525_PCLK_DIV0 << 2) |
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#if CONFIG_CPU == AS3525
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(AS3525_PCLK_DIV1 << 6) |
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#endif
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AS3525_PCLK_SEL);
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CGU_PERI |= CGU_ROM_ENABLE; /* needed for rebooting */
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#if 0 /* the GPIO clock is already enabled by the dualboot function */
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CGU_PERI |= CGU_GPIO_CLOCK_ENABLE;
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#endif
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/* enable timer interface for TIMER1 & TIMER2 */
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CGU_PERI |= CGU_TIMERIF_CLOCK_ENABLE;
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setup_vic();
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dma_init();
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}
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/* this is called after kernel and threading are initialized */
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void kernel_device_init(void)
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{
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mutex_init(&cpufreq_mtx);
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ascodec_init();
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/* Initialize power management settings */
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#ifdef HAVE_AS3543
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/* PLL: disable audio PLL, we use MCLK already */
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ascodec_write_pmu(0x1A, 7, 0x02);
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/* DCDC_Cntr: set switching speed of CVDD1/2 power supplies to 1 MHz,
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immediate change */
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ascodec_write_pmu(0x17, 7, 0x30);
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/* Out_Cntr2: set drive strength of 24 MHz and 32 kHz clocks to 1 mA */
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ascodec_write_pmu(0x1A, 2, 0xCC);
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/* CHGVBUS2: set VBUS threshold to 3.18V and EOC threshold to 30% CC */
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ascodec_write_pmu(0x19, 2, 0x41);
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/* PVDD1: set PVDD1 power supply to 2.5 V */
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ascodec_write_pmu(0x18, 1, 0x35);
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/* AVDD17: set AVDD17 power supply to 2.5V */
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ascodec_write_pmu(0x18, 7, 0x31);
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/* CVDD2: set CVDD2 power supply (digital for DAC/SD/etc) to 2.75V */
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ascodec_write_pmu(0x17, 2, 0x80 | 115);
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#else /* HAVE_AS3543 */
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ascodec_write(AS3514_CVDD_DCDC3, AS314_CP_DCDC3_SETTING);
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#endif /* HAVE_AS3543 */
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#ifndef BOOTLOADER
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/* setup isr for microsd monitoring and for fuzev2 scrollwheel irq */
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#if defined(HAVE_HOTSWAP) || \
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(defined(SANSA_FUZEV2) && !INCREASED_SCROLLWHEEL_POLLING)
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VIC_INT_ENABLE = (INTERRUPT_GPIOA);
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/* pin selection for irq happens in the drivers */
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#endif
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#if CONFIG_TUNER
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fmradio_i2c_init();
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#endif
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#endif /* !BOOTLOADER */
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check_model_variant();
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}
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void system_reboot(void)
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{
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backlight_hw_off();
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disable_irq();
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/* use watchdog to reset */
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CGU_PERI |= (CGU_WDOCNT_CLOCK_ENABLE | CGU_WDOIF_CLOCK_ENABLE);
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WDT_LOAD = 1; /* set counter to 1 */
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WDT_CONTROL = 3; /* enable watchdog counter & reset */
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while(1);
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}
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void system_exception_wait(void)
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{
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/* make sure lcd+backlight are on */
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_backlight_panic_on();
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/* make sure screen content is up to date */
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lcd_update();
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/* wait until button release (if a button is pressed) */
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while(button_read_device());
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/* then wait until next button press */
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while(!button_read_device());
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}
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int system_memory_guard(int newmode)
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{
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(void)newmode;
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return 0;
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}
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/* usecs may be at most 2^32/248 (17 seconds) for 248MHz max cpu freq */
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void udelay(unsigned usecs)
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{
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unsigned cycles_per_usec;
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unsigned delay;
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if (cpu_frequency == CPUFREQ_MAX) {
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cycles_per_usec = (CPUFREQ_MAX + 999999) / 1000000;
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} else {
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cycles_per_usec = (CPUFREQ_NORMAL + 999999) / 1000000;
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}
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delay = (usecs * cycles_per_usec + 3) / 4;
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asm volatile(
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"1: subs %0, %0, #1 \n" /* 1 cycle */
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" bne 1b \n" /* 3 cycles */
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: : "r"(delay)
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);
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}
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#ifndef BOOTLOADER
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#ifdef HAVE_ADJUSTABLE_CPU_FREQ
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bool set_cpu_frequency__lock(void)
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{
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if (get_processor_mode() != CPU_MODE_THREAD_CONTEXT)
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return false;
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mutex_lock(&cpufreq_mtx);
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return true;
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}
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void set_cpu_frequency__unlock(void)
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{
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mutex_unlock(&cpufreq_mtx);
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}
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#if CONFIG_CPU == AS3525
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void set_cpu_frequency(long frequency)
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{
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if (frequency == cpu_frequency)
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{
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/* avoid redundant activity */
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}
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else if(frequency == CPUFREQ_MAX)
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{
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#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
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/* Increasing frequency so boost voltage before change */
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ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_20));
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/* Some players run a bit low so use 1.175 volts instead of 1.20 */
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/* Wait for voltage to be at least 1.175v before making fclk > 200 MHz */
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while(adc_read(ADC_CVDD) < 470); /* 470 * .0025 = 1.175V */
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#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
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|
CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
|
|
(AS3525_FCLK_PREDIV << 2) |
|
|
AS3525_FCLK_SEL);
|
|
|
|
asm volatile(
|
|
"mrc p15, 0, r0, c1, c0 \n"
|
|
"orr r0, r0, #3<<30 \n" /* asynchronous bus clocking */
|
|
/* synchronous bus clocking had issues on some players */
|
|
"mcr p15, 0, r0, c1, c0 \n"
|
|
: : : "r0" );
|
|
|
|
cpu_frequency = CPUFREQ_MAX;
|
|
}
|
|
else
|
|
{
|
|
asm volatile(
|
|
"mrc p15, 0, r0, c1, c0 \n"
|
|
"bic r0, r0, #3<<30 \n" /* fastbus clocking */
|
|
"mcr p15, 0, r0, c1, c0 \n"
|
|
: : : "r0" );
|
|
|
|
/* FCLK is unused so put it to the lowest freq we can */
|
|
CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN);
|
|
|
|
#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
|
|
/* Decreasing frequency so reduce voltage after change */
|
|
ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
|
|
#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
|
|
|
|
cpu_frequency = CPUFREQ_NORMAL;
|
|
}
|
|
}
|
|
#else /* as3525v2 */
|
|
void set_cpu_frequency(long frequency)
|
|
{
|
|
if (frequency == cpu_frequency)
|
|
{
|
|
/* avoid redundant activity */
|
|
}
|
|
else if(frequency == CPUFREQ_MAX)
|
|
{
|
|
#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
|
|
/* Set CVDD1 power supply */
|
|
ascodec_write_pmu(0x17, 1, 0x80 | 47);
|
|
/* dely for voltage rising */
|
|
udelay(50);
|
|
#endif
|
|
CGU_PROC = ((AS3525_FCLK_POSTDIV << 4) |
|
|
(AS3525_FCLK_PREDIV << 2) |
|
|
AS3525_FCLK_SEL);
|
|
|
|
cpu_frequency = CPUFREQ_MAX;
|
|
}
|
|
else
|
|
{
|
|
CGU_PROC = ((AS3525_FCLK_POSTDIV_UNBOOSTED << 4) |
|
|
(AS3525_FCLK_PREDIV << 2) |
|
|
AS3525_FCLK_SEL);
|
|
|
|
cpu_frequency = CPUFREQ_NORMAL;
|
|
|
|
/* Set CVDD1 power supply */
|
|
#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
|
|
#if defined(SANSA_CLIPZIP)
|
|
ascodec_write_pmu(0x17, 1, 0x80 | 20);
|
|
#elif defined(SANSA_CLIPPLUS)
|
|
if (amsv2_variant)
|
|
ascodec_write_pmu(0x17, 1, 0x80 | 22);
|
|
else
|
|
ascodec_write_pmu(0x17, 1, 0x80 | 26);
|
|
#elif defined(SANSA_FUZEV2)
|
|
/*Some FuzeV2 devices have trouble reading SD at low voltage*/
|
|
ascodec_write_pmu(0x17, 1, 0x80 | 26);
|
|
#else
|
|
ascodec_write_pmu(0x17, 1, 0x80 | 22);
|
|
#endif
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#endif /* HAVE_ADJUSTABLE_CPU_FREQ */
|
|
#endif /* !BOOTLOADER */
|