As3525 v1/v2 Add power savings menu
Allow user to select cpu undervolt There have been quite a few issues across the SANSA AMS line related to CPU undervolting while most players show greatly increased runtime some crash. Rather than constanly upping the voltage we now have a setting with a safe value for all players and the option for lower voltages I plan to add a few other options here later such as disk timings and maybe some other clocks/experimental settings Added: Disk Low speed option for AS3525v2 devices cuts frequency to 12 MHz from 24 MHz Added: Disk Low speed option for AS3525v1 devices cuts frequency to 15.5 MHz from 31 MHz Added: I2c Low Speed AS3525 devices, should be bigger improvement for v1 devices Fixed: Debug menu for AS3525v2 No SDSLOT frequency, Showed IDE freq though it is unused Added: DBOP and SSP underclocking affects display on v1/v2 respectively Fixed: debug menu now has SSP frequency, and SSP_CPSR Update: made settings menu more generic Update: cleaned up code Added: Clip v1 & Fuze v1 didn't have HAVE_ADJUSTABLE_CPU_VOLTAGE. not sure why but, waiting on testing to confirm Added: C200v2 and E200v2 devices and HAVE_ADJUSTABLE_CPU_VOLTAGE. Fixed: v1 devices don't like display timing set lower (dbop) v1 devices don't have a divider set for ssp (causes divide by 0) Fixed: ClipZip display lags with Max SSP divider changed from 0xFE to 0x32 Fixed: v1 devices didn't work properly with highspeed sd cards Added code from http://gerrit.rockbox.org/r/#/c/1704/ Added powersave and IDE interface enable/disable Added: V2 devices now have powersave enabled on sd interface Update: cleaned up code, lang defines, added manual entries Update ssp clock mechanism added calculated ssp divider to clipzip Update turn display clock off when clip+ turns off display Fixed: clipzip wrong register for SSP clock Change-Id: I04137682243be92f0f8d8bf1cfa54fbb1965559b TODO: add other players?
This commit is contained in:
parent
400603abdf
commit
6f0320a953
23 changed files with 537 additions and 52 deletions
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@ -288,3 +288,7 @@ play_frequency
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#if defined(HAVE_BOOTDATA)
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boot_data
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#endif
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#if defined(CONFIG_POWER_SAVING)
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sys_powersaving
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#endif
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@ -13647,3 +13647,54 @@
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*: "Disable Touch"
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</voice>
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</phrase>
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<phrase>
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id: LANG_POWER_SAVING_MENU
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desc: system clock and voltage settings
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user: core
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<source>
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*: none
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sys_powersaving: "Power Saving"
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</source>
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<dest>
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*: none
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sys_powersaving: "Power Saving"
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</dest>
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<voice>
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*: none
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sys_powersaving: "Power Saving"
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</voice>
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</phrase>
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<phrase>
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id: LANG_CPU
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desc: system clock and voltage settings
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user: core
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<source>
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*: none
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sys_powersaving: "CPU"
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</source>
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<dest>
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*: none
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sys_powersaving: "CPU"
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</dest>
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<voice>
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*: none
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sys_powersaving: "CPU"
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</voice>
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</phrase>
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<phrase>
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id: LANG_I2C
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desc: system clock and voltage settings
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user: core
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<source>
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*: none
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sys_powersaving: "I2C"
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</source>
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<dest>
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*: none
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sys_powersaving: "I2C"
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</dest>
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<voice>
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*: none
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sys_powersaving: "I2C"
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</voice>
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</phrase>
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@ -295,6 +295,36 @@ MAKE_MENU(disk_menu, ID2P(LANG_DISK_MENU), 0, Icon_NOICON,
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);
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#endif
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#ifdef CONFIG_POWER_SAVING
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#if (CONFIG_POWER_SAVING & POWERSV_CPU)
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MENUITEM_SETTING(cpu_powersave, &global_settings.cpu_powersave, NULL);
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISK)
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MENUITEM_SETTING(disk_powersave, &global_settings.disk_powersave, NULL);
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_I2C)
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MENUITEM_SETTING(i2c_powersave, &global_settings.i2c_powersave, NULL);
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISP)
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MENUITEM_SETTING(disp_powersave, &global_settings.disp_powersave, NULL);
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#endif
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MAKE_MENU(power_save_menu, ID2P(LANG_POWER_SAVING_MENU), 0, Icon_NOICON,
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#if (CONFIG_POWER_SAVING & POWERSV_CPU)
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&cpu_powersave,
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISK)
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&disk_powersave,
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_I2C)
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&i2c_powersave,
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISP)
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&disp_powersave,
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#endif
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);
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#endif /* ifdef CONFIG_POWER_SAVING */
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/* Limits menu */
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MENUITEM_SETTING(max_files_in_dir, &global_settings.max_files_in_dir, NULL);
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MENUITEM_SETTING(max_files_in_playlist, &global_settings.max_files_in_playlist, NULL);
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@ -412,6 +442,11 @@ MAKE_MENU(system_menu, ID2P(LANG_SYSTEM),
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&disk_menu,
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#endif
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&limits_menu,
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#if defined(CONFIG_POWER_SAVING)
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&power_save_menu,
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#endif
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#ifdef HAVE_QUICKSCREEN
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&shortcuts_replaces_quickscreen,
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#endif
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@ -860,6 +860,25 @@ struct user_settings
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int governor;
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int usb_mode;
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#endif
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#ifdef CONFIG_POWER_SAVING
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#if (CONFIG_POWER_SAVING & POWERSV_CPU)
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bool cpu_powersave;
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISK)
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bool disk_powersave;
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_I2C)
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bool i2c_powersave;
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISP)
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bool disp_powersave;
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#endif
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#endif /*defined(CONFIG_POWER_SAVING)*/
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};
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/** global variables **/
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@ -2246,7 +2246,43 @@ const struct settings_list settings[] = {
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ID2P(LANG_IBASSO_USB_MODE_CHARGE),
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ID2P(LANG_IBASSO_USB_MODE_ADB)),
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#endif
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};
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#ifdef CONFIG_POWER_SAVING
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#if (CONFIG_POWER_SAVING & POWERSV_CPU)
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OFFON_SETTING(0,
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cpu_powersave,
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LANG_CPU,
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false,
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"cpu powersave",
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cpu_set_powersave),
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISK)
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OFFON_SETTING(0,
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disk_powersave,
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LANG_DISK_MENU,
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false,
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"disk powersave",
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disk_set_powersave),
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_DISP)
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OFFON_SETTING(0,
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disp_powersave,
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LANG_DISPLAY,
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false,
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"disp powersave",
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disp_set_powersave),
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#endif
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#if (CONFIG_POWER_SAVING & POWERSV_I2C)
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OFFON_SETTING(0,
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i2c_powersave,
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LANG_I2C,
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false,
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"i2c powersave",
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i2c_set_powersave),
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#endif
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#endif /*defined(CONFIG_POWER_SAVING)*/
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};/*struct settings_list settings*/
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const int nb_settings = sizeof(settings)/sizeof(*settings);
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@ -168,6 +168,12 @@
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#define SONY_NWZA860_PAD 64 /* The NWZ-A860 is too different (touchscreen) */
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#define AGPTEK_ROCKER_PAD 65
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/* CONFIG_POWER_SAVE combinable bit flags*/
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#define POWERSV_CPU 0x1
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#define POWERSV_I2C 0x2
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#define POWERSV_DISK 0x4
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#define POWERSV_DISP 0x8
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/* CONFIG_REMOTE_KEYPAD */
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#define H100_REMOTE 1
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#define H300_REMOTE 2
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@ -193,6 +193,14 @@
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -186,6 +186,14 @@
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -206,6 +206,11 @@
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK | POWERSV_DISP)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -200,6 +200,11 @@
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -205,6 +205,11 @@
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK | POWERSV_DISP)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -213,6 +213,14 @@
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -219,6 +219,14 @@
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/* Define this if you have adjustable CPU frequency */
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#define HAVE_ADJUSTABLE_CPU_FREQ
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -224,6 +224,11 @@
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/*define this to enable CPU voltage scaling on AMS devices*/
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#define HAVE_ADJUSTABLE_CPU_VOLTAGE
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#ifndef BOOTLOADER
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/*define this with flags for power saving options device supports*/
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#define CONFIG_POWER_SAVING (POWERSV_CPU | POWERSV_I2C | POWERSV_DISK)
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#endif
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#define BOOTFILE_EXT "sansa"
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#define BOOTFILE "rockbox." BOOTFILE_EXT
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#define BOOTDIR "/.rockbox"
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@ -623,11 +623,25 @@ void i2c_init(void)
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/* required function but called too late for our needs */
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}
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static void i2c_set_prescaler(unsigned int prescaler)
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{
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int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
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/* must be on to write regs */
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bool i2c_enabled = bitset32(&CGU_PERI, CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE) &
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CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE;
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I2C2_CPSR0 = prescaler & 0xFF; /* 8 lsb */
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I2C2_CPSR1 = (prescaler >> 8) & 0x3; /* 2 msb */
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if (!i2c_enabled) /* put it back how we found it */
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bitclr32(&CGU_PERI, CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE);
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restore_irq(oldlevel);
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}
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/* initialises the internal i2c bus and prepares for transfers to the codec */
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void ascodec_init(void)
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{
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int prescaler;
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ll_init(&req_list);
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mutex_init(&as_mtx);
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ascodec_async_init(&as_audio_req, ascodec_int_audio_cb, 0);
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bitset32(&CGU_PERI, CGU_I2C_AUDIO_MASTER_CLOCK_ENABLE);
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/* prescaler for i2c clock */
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prescaler = AS3525_I2C_PRESCALER;
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I2C2_CPSR0 = prescaler & 0xFF; /* 8 lsb */
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I2C2_CPSR1 = (prescaler >> 8) & 0x3; /* 2 msb */
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i2c_set_prescaler(AS3525_I2C_PRESCALER);
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/* set i2c slave address of codec part */
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I2C2_SLAD0 = AS3514_I2C_ADDR << 1;
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@ -690,3 +702,12 @@ void ams_i2c_get_debug_cpsr(unsigned int *i2c_cpsr)
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restore_irq(oldlevel);
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}
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#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_I2C)
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/* declared in system-as3525.c */
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void ams_i2c_set_low_speed(bool slow)
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{
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i2c_set_prescaler(slow ? AS3525_I2C_PRESCALER_MAX : AS3525_I2C_PRESCALER);
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}
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#endif
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#endif /* CONFIG_CPU */
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/* PCLK as Source */
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#define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
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#define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
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#define AS3525_I2C_FREQ 400000
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#define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
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#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
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#define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */
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#define AS3525_SSP_FREQ 12000000
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#define AS3525_DBOP_DIV (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) /*div=1/(n+1)*/
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#define AS3525_I2C_PRESCALER CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)
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#define AS3525_I2C_PRESCALER_MAX 0xFF | 0x300 /* Max value for prescaler */
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#define AS3525_I2C_FREQ 400000
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#define AS3525_SD_IDENT_DIV ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1)
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#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
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#define AS3525_SSP_PRESCALER ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ) + 1) & ~1) /* must be an even number */
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#if LCD_DEPTH > 1
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#define AS3525_SSP_PRESCALER_MAX ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN) + 1) & ~1)/* must be an even number */
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#define AS3525_SSP_FREQ_MIN 2000000 /* 2 MHz gives a decent refresh rate on clipzip*/
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#else
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#define AS3525_SSP_PRESCALER_MAX 0xFE & ~1 /*Max value for divider - must be an even number */
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#define AS3525_SSP_FREQ_MIN AS3525_SSP_FREQ /* No set minimum we just use max divider */
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#endif
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#define AS3525_SSP_FREQ 12000000
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#define AS3525_IDE_SEL AS3525_CLK_PLLA /* Input Source */
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#define AS3525_IDE_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1)/*div=1/(n+1)*/
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#define AS3525_IDE_DIV_MAX 0xF /* Max value for divider */
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#if CONFIG_CPU == AS3525v2
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#define AS3525_MS_FREQ 120000000
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#define AS3525_MS_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_MS_FREQ) -1)
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#define AS3525_SDSLOT_FREQ 24000000
|
||||
#define AS3525_SDSLOT_DIV (CLK_DIV(AS3525_PLLA_FREQ, AS3525_SDSLOT_FREQ) -1)
|
||||
#define AS3525_SDSLOT_DIV_MAX 0xF /* Max value for divider */
|
||||
#define AS3525_IDE_FREQ 80000000
|
||||
#else
|
||||
#define AS3525_IDE_FREQ 50000000 /* The OF uses 66MHz maximal freq */
|
||||
|
@ -211,6 +221,10 @@
|
|||
#error SSP frequency is too low : clock divider will not fit !
|
||||
#endif
|
||||
|
||||
#if (((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SSP_FREQ_MIN)) + 1 ) & ~1) >= (1<<8) /* 8 bits */
|
||||
#error SSP_MIN frequency is too low : clock divider will not fit !
|
||||
#endif
|
||||
|
||||
/* AS3525_SD_IDENT_FREQ */
|
||||
#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
|
||||
#error SD IDENTIFICATION frequency is too low : clock divider will not fit !
|
||||
|
|
|
@ -26,11 +26,25 @@
|
|||
#include "system.h"
|
||||
#include "cpu.h"
|
||||
|
||||
static void ssp_set_prescaler(unsigned int prescaler)
|
||||
{
|
||||
int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
|
||||
/* must be on to write regs */
|
||||
bool ssp_enabled = bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE) &
|
||||
CGU_SSP_CLOCK_ENABLE;
|
||||
SSP_CPSR = prescaler;
|
||||
|
||||
if (!ssp_enabled) /* put it back how we found it */
|
||||
bitclr32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE);
|
||||
|
||||
restore_irq(oldlevel);
|
||||
}
|
||||
|
||||
int lcd_hw_init(void)
|
||||
{
|
||||
bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE);
|
||||
|
||||
SSP_CPSR = AS3525_SSP_PRESCALER; /* OF = 0x10 */
|
||||
ssp_set_prescaler(AS3525_SSP_PRESCALER); /* OF = 0x10 */
|
||||
SSP_CR0 = (1<<7) | (1<<6) | 7; /* Motorola SPI frame format, 8 bits */
|
||||
SSP_CR1 = (1<<3) | (1<<1); /* SSP Operation enabled */
|
||||
SSP_IMSC = 0; /* No interrupts */
|
||||
|
@ -115,3 +129,10 @@ void lcd_enable_power(bool onoff)
|
|||
#endif
|
||||
}
|
||||
|
||||
#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISP)
|
||||
/* declared in system-as3525.c */
|
||||
void ams_ssp_set_low_speed(bool slow)
|
||||
{
|
||||
ssp_set_prescaler(slow ? AS3525_SSP_PRESCALER_MAX : AS3525_SSP_PRESCALER);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -35,12 +35,26 @@ static int lcd_type;
|
|||
static bool lcd_enabled;
|
||||
#endif
|
||||
|
||||
static void ssp_set_prescaler(unsigned int prescaler)
|
||||
{
|
||||
int oldlevel = disable_interrupt_save(IRQ_FIQ_STATUS);
|
||||
/* must be on to write regs */
|
||||
bool ssp_enabled = bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE) &
|
||||
CGU_SSP_CLOCK_ENABLE;
|
||||
SSP_CPSR = prescaler;
|
||||
|
||||
if (!ssp_enabled) /* put it back how we found it */
|
||||
bitclr32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE);
|
||||
|
||||
restore_irq(oldlevel);
|
||||
}
|
||||
|
||||
/* initialises the host lcd hardware, returns the lcd type */
|
||||
static int lcd_hw_init(void)
|
||||
{
|
||||
/* configure SSP */
|
||||
bitset32(&CGU_PERI, CGU_SSP_CLOCK_ENABLE);
|
||||
SSP_CPSR = 4; /* TODO: use AS3525_SSP_PRESCALER, OF uses 8 */
|
||||
ssp_set_prescaler(AS3525_SSP_PRESCALER); /* OF = 0x8 */
|
||||
SSP_CR0 = (0 << 8) | /* SCR, serial clock rate divider = 1 */
|
||||
(1 << 7) | /* SPH, phase = 1 */
|
||||
(1 << 6) | /* SPO, polarity = 1 */
|
||||
|
@ -437,3 +451,11 @@ void lcd_update(void)
|
|||
{
|
||||
lcd_update_rect(0, 0, LCD_WIDTH, LCD_HEIGHT);
|
||||
}
|
||||
|
||||
#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISP)
|
||||
/* declared in system-as3525.c */
|
||||
void ams_ssp_set_low_speed(bool slow)
|
||||
{
|
||||
ssp_set_prescaler(slow ? AS3525_SSP_PRESCALER_MAX : AS3525_SSP_PRESCALER);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -89,6 +89,8 @@
|
|||
| MCI_CMD_CRC_FAIL)
|
||||
|
||||
#define MCI_FIFO(i) ((unsigned long *) (pl180_base[i]+0x80))
|
||||
|
||||
#define IDE_INTERFACE_CLK (1<<6) /* non AHB interface */
|
||||
/* volumes */
|
||||
#define INTERNAL_AS3525 0 /* embedded SD card */
|
||||
#define SD_SLOT_AS3525 1 /* SD slot if present */
|
||||
|
@ -109,7 +111,8 @@ static void init_pl180_controller(const int drive);
|
|||
|
||||
static tCardInfo card_info[NUM_DRIVES];
|
||||
|
||||
/* maximum timeouts recommanded in the SD Specification v2.00 */
|
||||
/* maximum timeouts recommended in the SD Specification v2.00 */
|
||||
/* MCI_DATA_TIMER register data timeout in card bus clock periods */
|
||||
#define SD_MAX_READ_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 100) /* 100 ms */
|
||||
#define SD_MAX_WRITE_TIMEOUT ((AS3525_PCLK_FREQ) / 1000 * 250) /* 250 ms */
|
||||
|
||||
|
@ -143,7 +146,17 @@ static unsigned char *uncached_buffer = AS3525_UNCACHED_ADDR(&aligned_buffer[0])
|
|||
|
||||
static inline void mci_delay(void) { udelay(1000) ; }
|
||||
|
||||
static void enable_controller(bool on)
|
||||
static inline bool card_detect_target(void)
|
||||
{
|
||||
#if defined(HAVE_MULTIDRIVE)
|
||||
return !(GPIOA_PIN(2));
|
||||
#else
|
||||
return false;
|
||||
#endif
|
||||
}
|
||||
|
||||
#if defined(HAVE_MULTIDRIVE) || defined(HAVE_HOTSWAP)
|
||||
static void enable_controller_mci(bool on)
|
||||
{
|
||||
|
||||
#if defined(HAVE_BUTTON_LIGHT) && defined(HAVE_MULTIDRIVE)
|
||||
|
@ -197,17 +210,33 @@ static void enable_controller(bool on)
|
|||
#endif
|
||||
}
|
||||
}
|
||||
#endif /* defined(HAVE_MULTIDRIVE) || defined(HAVE_HOTSWAP) */
|
||||
|
||||
static inline bool card_detect_target(void)
|
||||
/* AMS v1 have two different drive interfaces MCI_SD(XPD) and GGU_IDE */
|
||||
static void enable_controller(bool on, const int drive)
|
||||
{
|
||||
#if defined(HAVE_MULTIDRIVE)
|
||||
return !(GPIOA_PIN(2));
|
||||
#else
|
||||
return false;
|
||||
|
||||
if (drive == INTERNAL_AS3525)
|
||||
{
|
||||
#ifndef BOOTLOADER
|
||||
if (on)
|
||||
{
|
||||
bitset32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE);
|
||||
CGU_IDE |= IDE_INTERFACE_CLK; /* interface enable */
|
||||
}
|
||||
else
|
||||
{
|
||||
CGU_IDE &= ~(IDE_INTERFACE_CLK); /* interface disable */
|
||||
bitclr32(&CGU_PERI, CGU_NAF_CLOCK_ENABLE);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#if defined(HAVE_MULTIDRIVE) || defined(HAVE_HOTSWAP)
|
||||
else
|
||||
enable_controller_mci(on);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
#ifdef HAVE_HOTSWAP
|
||||
static int sd1_oneshot_callback(struct timeout *tmo)
|
||||
{
|
||||
|
@ -326,6 +355,7 @@ static bool send_cmd(const int drive, const int cmd, const int arg,
|
|||
return false;
|
||||
}
|
||||
|
||||
/* MCI_CLOCK = MCLK / 2x(ClkDiv[bits 7:0]+1) */
|
||||
#define MCI_FULLSPEED (MCI_CLOCK_ENABLE | MCI_CLOCK_BYPASS) /* MCLK */
|
||||
#define MCI_HALFSPEED (MCI_CLOCK_ENABLE) /* MCLK/2 */
|
||||
#define MCI_QUARTERSPEED (MCI_CLOCK_ENABLE | 1) /* MCLK/4 */
|
||||
|
@ -345,7 +375,7 @@ static int sd_init_card(const int drive)
|
|||
/* 100 - 400kHz clock required for Identification Mode */
|
||||
/* Start of Card Identification Mode ************************************/
|
||||
|
||||
/* CMD0 Go Idle */
|
||||
/* CMD0 Go Idle -- all card functions switch back to default */
|
||||
if(!send_cmd(drive, SD_GO_IDLE_STATE, 0, MCI_NO_RESP, NULL))
|
||||
return -1;
|
||||
mci_delay();
|
||||
|
@ -393,10 +423,10 @@ static int sd_init_card(const int drive)
|
|||
|
||||
if(sd_wait_for_tran_state(drive))
|
||||
return -6;
|
||||
/* CMD6 */
|
||||
/* CMD6 0xf indicates no influence, [3:0],0x1 - HS Access*/
|
||||
if(!send_cmd(drive, SD_SWITCH_FUNC, 0x80fffff1, MCI_NO_RESP, NULL))
|
||||
return -7;
|
||||
sleep(HZ/10);
|
||||
sleep(HZ/10);/* need to wait at least 8 clock periods */
|
||||
|
||||
/* go back to STBY state so we can read csd */
|
||||
/* CMD7 w/rca=0: Deselect card to put it in STBY state */
|
||||
|
@ -517,7 +547,7 @@ static void init_pl180_controller(const int drive)
|
|||
int sd_init(void)
|
||||
{
|
||||
int ret;
|
||||
CGU_IDE = (1<<6) /* enable non AHB interface*/
|
||||
CGU_IDE = IDE_INTERFACE_CLK /* enable interface */
|
||||
| (AS3525_IDE_DIV << 2)
|
||||
| AS3525_CLK_PLLA; /* clock source = PLLA */
|
||||
|
||||
|
@ -540,7 +570,9 @@ int sd_init(void)
|
|||
/* init mutex */
|
||||
mutex_init(&sd_mtx);
|
||||
|
||||
enable_controller(false);
|
||||
for (int i = 0; i < NUM_DRIVES ; i++)
|
||||
enable_controller(false, i);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
@ -656,7 +688,7 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start,
|
|||
unsigned long response;
|
||||
bool aligned = !((uintptr_t)buf & (CACHEALIGN_SIZE - 1));
|
||||
|
||||
enable_controller(true);
|
||||
enable_controller(true, drive);
|
||||
led(true);
|
||||
|
||||
if (card_info[drive].initialized <= 0)
|
||||
|
@ -692,27 +724,21 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start,
|
|||
else
|
||||
discard_dcache_range(buf, count * SECTOR_SIZE);
|
||||
}
|
||||
|
||||
while(count)
|
||||
const int cmd = write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
|
||||
while(count > 0)
|
||||
{
|
||||
/* 128 * 512 = 2^16, and doesn't fit in the 16 bits of DATA_LENGTH
|
||||
* register, so we have to transfer maximum 127 sectors at a time. */
|
||||
unsigned int transfer = (count >= 128) ? 127 : count; /* sectors */
|
||||
void *dma_buf;
|
||||
const int cmd =
|
||||
write ? SD_WRITE_MULTIPLE_BLOCK : SD_READ_MULTIPLE_BLOCK;
|
||||
|
||||
unsigned long bank_start = start;
|
||||
unsigned long status;
|
||||
|
||||
/* Only switch banks for internal storage */
|
||||
if(drive == INTERNAL_AS3525)
|
||||
{
|
||||
unsigned int bank = 0;
|
||||
while(bank_start >= BLOCKS_PER_BANK)
|
||||
{
|
||||
bank_start -= BLOCKS_PER_BANK;
|
||||
bank++;
|
||||
}
|
||||
unsigned int bank = bank_start / BLOCKS_PER_BANK;
|
||||
bank_start -= bank * BLOCKS_PER_BANK;
|
||||
|
||||
/* Switch bank if needed */
|
||||
if(card_info[INTERNAL_AS3525].current_bank != bank)
|
||||
|
@ -770,10 +796,7 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start,
|
|||
/*Small delay for writes prevents data crc failures at lower freqs*/
|
||||
#ifdef HAVE_MULTIDRIVE
|
||||
if((drive == SD_SLOT_AS3525) && !hs_card)
|
||||
{
|
||||
int write_delay = 125;
|
||||
while(write_delay--);
|
||||
}
|
||||
udelay(4);
|
||||
#endif
|
||||
}
|
||||
else
|
||||
|
@ -804,7 +827,7 @@ static int sd_transfer_sectors(IF_MD(int drive,) unsigned long start,
|
|||
|
||||
last_disk_activity = current_tick;
|
||||
|
||||
if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &status))
|
||||
if(!send_cmd(drive, SD_STOP_TRANSMISSION, 0, MCI_RESP, &response))
|
||||
{
|
||||
ret = -4*20;
|
||||
goto sd_transfer_error;
|
||||
|
@ -831,7 +854,7 @@ sd_transfer_error:
|
|||
sd_transfer_error_nodma:
|
||||
|
||||
led(false);
|
||||
enable_controller(false);
|
||||
enable_controller(false, drive);
|
||||
|
||||
if (ret) /* error */
|
||||
card_info[drive].initialized = 0;
|
||||
|
@ -922,12 +945,18 @@ void ams_sd_get_debug_info(struct ams_sd_debug_info *info)
|
|||
#define MCI_SD *((volatile unsigned long *)(SD_MCI_BASE + 0x04))
|
||||
|
||||
mutex_lock(&sd_mtx);
|
||||
enable_controller(true); /* must be on to read regs */
|
||||
|
||||
for (int i = 0; i < NUM_DRIVES ; i++)
|
||||
enable_controller(true, i); /* must be on to read regs */
|
||||
|
||||
info->mci_nand = MCI_NAND;
|
||||
#ifdef HAVE_MULTIDRIVE
|
||||
info->mci_sd = MCI_SD;
|
||||
#endif
|
||||
enable_controller(false);
|
||||
|
||||
for (int i = 0; i < NUM_DRIVES ; i++)
|
||||
enable_controller(false, i);
|
||||
|
||||
mutex_unlock(&sd_mtx);
|
||||
}
|
||||
|
||||
|
@ -948,10 +977,10 @@ int sd_event(long id, intptr_t data)
|
|||
|
||||
if (id == SYS_HOTSWAP_INSERTED)
|
||||
{
|
||||
enable_controller(true);
|
||||
enable_controller(true, data);
|
||||
init_pl180_controller(data);
|
||||
rc = sd_init_card(data);
|
||||
enable_controller(false);
|
||||
enable_controller(false, data);
|
||||
}
|
||||
|
||||
mutex_unlock(&sd_mtx);
|
||||
|
@ -968,3 +997,42 @@ int sd_event(long id, intptr_t data)
|
|||
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISK)
|
||||
/* declared in system-as3525.c */
|
||||
void ams_sd_set_low_speed(bool slow)
|
||||
{
|
||||
/* block access while speed is changed */
|
||||
mutex_lock(&sd_mtx);
|
||||
enable_controller(true, INTERNAL_AS3525);
|
||||
|
||||
/* After a data write, data cannot be written to MCI_CLOCK
|
||||
for 3 MCLK periods + 2 PCLK periods. ~10us worst case
|
||||
*/
|
||||
udelay(100);
|
||||
if (slow)
|
||||
{
|
||||
/* only affects internal drive clock speed*/
|
||||
CGU_IDE = (CGU_IDE & ~(0xF << 2)) | (AS3525_IDE_DIV_MAX << 2);
|
||||
/* power save is enabled for the sd card(s) */
|
||||
for (int i = 0; i < NUM_DRIVES ; i++)
|
||||
{
|
||||
if (i != INTERNAL_AS3525 && (MCI_CLOCK(i) & MCI_CLOCK_POWERSAVE) == 0)
|
||||
MCI_CLOCK(i) |= MCI_CLOCK_POWERSAVE;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Full Speed */
|
||||
CGU_IDE = (CGU_IDE & ~(0xF << 2)) | (AS3525_IDE_DIV << 2);
|
||||
for (int i = 0; i < NUM_DRIVES ; i++)
|
||||
{
|
||||
if (i != INTERNAL_AS3525 && (MCI_CLOCK(i) & MCI_CLOCK_POWERSAVE) != 0)
|
||||
MCI_CLOCK(i) = (MCI_CLOCK(i) & ~MCI_CLOCK_POWERSAVE);
|
||||
}
|
||||
}
|
||||
enable_controller(false, INTERNAL_AS3525);
|
||||
mutex_unlock(&sd_mtx);
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
@ -488,7 +488,7 @@ static int sd_init_card(const int drive)
|
|||
card_info[drive].initialized = 0;
|
||||
card_info[drive].rca = 0;
|
||||
|
||||
/* assume 24 MHz clock / 60 = 400 kHz */
|
||||
/* assume 24 MHz clock / (2x)60 = 200 kHz */
|
||||
MCI_CLKDIV = (MCI_CLKDIV & ~(0xFF)) | 0x3C; /* CLK_DIV_0 : bits 7:0 */
|
||||
|
||||
/* 100 - 400kHz clock required for Identification Mode */
|
||||
|
@ -957,3 +957,27 @@ int sd_event(long id, intptr_t data)
|
|||
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_DISK)
|
||||
/* declared in system-as3525.c */
|
||||
void ams_sd_set_low_speed(bool slow)
|
||||
{
|
||||
/* block access while speed is changed */
|
||||
mutex_lock(&sd_mtx);
|
||||
enable_controller(true);
|
||||
if (slow)
|
||||
{
|
||||
CGU_SDSLOT = (CGU_SDSLOT & ~(0xF << 2)) | (AS3525_SDSLOT_DIV_MAX << 2);
|
||||
/* power save is enabled for the sd card(s) ASSUMES CRD0 is int drive! */
|
||||
MCI_CLKENA |= (CCLK_LP_CRD1 | CCLK_LP_CRD2 | CCLK_LP_CRD3);
|
||||
}
|
||||
else
|
||||
{
|
||||
/* Full Speed */
|
||||
CGU_SDSLOT = (CGU_SDSLOT & ~(0xF << 2)) | (AS3525_SDSLOT_DIV << 2);
|
||||
MCI_CLKENA = (MCI_CLKENA & ~(CCLK_LP_CRD1 | CCLK_LP_CRD2 | CCLK_LP_CRD3));
|
||||
}
|
||||
enable_controller(false);
|
||||
mutex_unlock(&sd_mtx);
|
||||
}
|
||||
#endif
|
||||
|
|
|
@ -52,6 +52,29 @@ struct mutex cpufreq_mtx;
|
|||
#define default_interrupt(name) \
|
||||
extern __attribute__((weak,alias("UIRQ"))) void name (void)
|
||||
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
/* Powersave functions either manipulate the system directly
|
||||
or pass enabled flag on to these specific functions
|
||||
dis/enabling powersaving for the selected subsystem
|
||||
*/
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_CPU)
|
||||
/*cpu_set_powersave*/
|
||||
#include "settings.h"
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_DISP)
|
||||
/*disp_set_powersave*/
|
||||
void ams_ssp_set_low_speed(bool slow); /*lcd-clip-plus.c & lcd-clipzip.c*/
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_DISK)
|
||||
/*disk_set_powersave*/
|
||||
void ams_sd_set_low_speed(bool slow); /* sd-as3525.c & sd-as3525v2.c */
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_I2C)
|
||||
/*i2c_set_powersave*/
|
||||
void ams_i2c_set_low_speed(bool slow); /* ascodec-as3525.c*/
|
||||
#endif
|
||||
#endif /*CONFIG_POWER_SAVING*/
|
||||
|
||||
#if CONFIG_USBOTG != USBOTG_DESIGNWARE
|
||||
static void UIRQ (void) __attribute__((interrupt ("IRQ")));
|
||||
#endif
|
||||
|
@ -422,6 +445,39 @@ void udelay(unsigned usecs)
|
|||
);
|
||||
}
|
||||
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_CPU)
|
||||
void cpu_set_powersave(bool enabled)
|
||||
{
|
||||
/*global_settings.cpu_powersave*/
|
||||
/*handled in: set_cpu_frequency()*/
|
||||
(void) enabled;
|
||||
}
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_DISK)
|
||||
void disk_set_powersave(bool enabled)
|
||||
{
|
||||
/*global_settings.disk_powersave*/
|
||||
ams_sd_set_low_speed(enabled);
|
||||
}
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_DISP)
|
||||
void disp_set_powersave(bool enabled)
|
||||
{
|
||||
/*global_settings.disp_powersave*/
|
||||
ams_ssp_set_low_speed(enabled);
|
||||
}
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_I2C)
|
||||
void i2c_set_powersave(bool enabled)
|
||||
{
|
||||
/*global_settings.i2c_powersave*/
|
||||
ams_i2c_set_low_speed(enabled);
|
||||
}
|
||||
#endif
|
||||
#endif /*defined(CONFIG_POWER_SAVING)*/
|
||||
|
||||
|
||||
#ifndef BOOTLOADER
|
||||
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
||||
bool set_cpu_frequency__lock(void)
|
||||
|
@ -481,7 +537,12 @@ void set_cpu_frequency(long frequency)
|
|||
CGU_PROC = ((0xf << 4) | (0x3 << 2) | AS3525_CLK_MAIN);
|
||||
|
||||
#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
|
||||
/* Decreasing frequency so reduce voltage after change */
|
||||
/* Decreasing frequency so reduce voltage after change */
|
||||
#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_CPU)
|
||||
if (!global_settings.cpu_powersave)
|
||||
ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_15));
|
||||
else
|
||||
#endif
|
||||
ascodec_write(AS3514_CVDD_DCDC3, (AS314_CP_DCDC3_SETTING | CVDD_1_10));
|
||||
#endif /* HAVE_ADJUSTABLE_CPU_VOLTAGE */
|
||||
|
||||
|
@ -519,6 +580,13 @@ void set_cpu_frequency(long frequency)
|
|||
|
||||
/* Set CVDD1 power supply */
|
||||
#ifdef HAVE_ADJUSTABLE_CPU_VOLTAGE
|
||||
#if defined(CONFIG_POWER_SAVING) && (CONFIG_POWER_SAVING & POWERSV_CPU)
|
||||
if (!global_settings.cpu_powersave)
|
||||
{
|
||||
ascodec_write_pmu(0x17, 1, 0x80 | 26);
|
||||
return;
|
||||
}
|
||||
#endif
|
||||
#if defined(SANSA_CLIPZIP)
|
||||
ascodec_write_pmu(0x17, 1, 0x80 | 20);
|
||||
#elif defined(SANSA_CLIPPLUS)
|
||||
|
|
|
@ -73,6 +73,26 @@ static inline void mdelay(unsigned msecs)
|
|||
void usb_insert_int(void);
|
||||
void usb_remove_int(void);
|
||||
|
||||
|
||||
#ifdef CONFIG_POWER_SAVING
|
||||
/* Powersave functions either manipulate the system directly
|
||||
or pass enabled flag on to the devices specific function
|
||||
dis/enabling powersaving for the selected subsystem
|
||||
*/
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_CPU)
|
||||
void cpu_set_powersave(bool enabled);
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_DISP)
|
||||
void disp_set_powersave(bool enabled);
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_DISK)
|
||||
void disk_set_powersave(bool enabled);
|
||||
#endif
|
||||
#if (CONFIG_POWER_SAVING & POWERSV_I2C)
|
||||
void i2c_set_powersave(bool enabled);
|
||||
#endif
|
||||
#endif /*CONFIG_POWER_SAVING*/
|
||||
|
||||
#ifdef HAVE_ADJUSTABLE_CPU_FREQ
|
||||
#define CPU_BOOST_LOCK_DEFINED
|
||||
|
||||
|
|
|
@ -297,6 +297,30 @@ therefore result in better runtime.
|
|||
\end{description}
|
||||
} %\nopt{HAS_BUTTON_HOLD}
|
||||
|
||||
\opt{CONFIG_POWER_SAVING}{
|
||||
\subsection{Power Saving}
|
||||
These options allow users to increase runtime by lowering performance
|
||||
of select subsystems. Certain options may \emph{not} be applicable to your
|
||||
\dap{} or may cause undesired operation to your particular use case.
|
||||
|
||||
\emph{WARNING!} While every effort has been made to ensure the safety of these
|
||||
options, due to manufacturing variance some options may cause unwanted side
|
||||
effects, cause the \dap{} to crash or (while unlikely) even \emph{destroy}
|
||||
your \dap{}. \emph{PROCEED WITH CAUTION}
|
||||
|
||||
\begin{description}
|
||||
|
||||
\item[CPU]
|
||||
Allows lower voltages or cpu speed when enabled.
|
||||
\item[Disk]
|
||||
Allows slower disk operations when enabled.
|
||||
\item[I2C]
|
||||
Allows slower clocking of I2C device bus when enabled.
|
||||
\item[Display]
|
||||
Allows slower screen refresh rates when enabled.
|
||||
|
||||
\end{description}
|
||||
} %\opt{CONFIG_POWER_SAVING}
|
||||
|
||||
\opt{usb_hid}{
|
||||
\subsection{\label{ref:USB_HID}USB HID}
|
||||
|
|
Loading…
Reference in a new issue