393 lines
12 KiB
ArmAsm
393 lines
12 KiB
ArmAsm
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Linus Nielsen Feltzing
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "cpu.h"
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.section .startup,"ax",@progbits
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.global start
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start:
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#if defined(BOOTLOADER) && defined(HAVE_DUALBOOT) \
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&& (defined(IAUDIO_X5) || defined(IAUDIO_M5))
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/* 8 byte dualboot signature */
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bra.b 1f /* 0x6006 */
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.short 0x4442 /* DB */
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#if defined(IAUDIO_X5)
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.long 0x69617835 /* iax5 */
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#elif defined(IAUDIO_M5)
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.long 0x69616d35 /* iam5 */
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#else
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#error Dualboot signature not defined
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#endif
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1:
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/* As the control registers are write-only, we're relying on MBAR2 being */
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/* set up correctly by the preloader for button check */
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/* Only use scratch regs until we're sure that we will boot rockbox */
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lea MBAR2, %a1
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move.l (%a1), %a0 /* store GPIO_READ result for button check in main() */
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tst.b 0x30000000 /* preloader sets this to 1
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if woke up due to RTC alarm */
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bne .loadrockbox
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/* Wait ~3 seconds for ON-button release. We need roughly 300ns per
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iteration, so we check 10000000 times to reach the desired delay */
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move.l #10000000, %d0
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.on_button_test:
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move.l (%a1), %d1 /* GPIO_READ */
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and.l #0x06000000, %d1 /* Check main (bit 25=0) and remote (bit 26=0) */
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cmp.l #0x06000000, %d1 /* ON buttons simultaneously */
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beq.b .loadrockbox
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subq.l #1, %d0
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bne.b .on_button_test
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.loadoriginal:
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jmp 0x10010
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.loadrockbox:
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move.l %a0, %d7 /* keep initial GPIO_READ value in %d7 for now */
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#endif /* defined(BOOTLOADER && defined(HAVE_DUALBOOT)
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&& (defined(IAUDIO_X5) || defined(IAUDIO_M5)) */
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move.w #0x2700,%sr
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move.l #vectors,%d0
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movec.l %d0,%vbr
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move.l #MBAR+1,%d0
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movec.l %d0,%mbar
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move.l #MBAR2+1,%d0
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movec.l %d0,%mbar2
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lea MBAR,%a0
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lea MBAR2,%a1
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#if defined(BOOTLOADER) && !defined(HAVE_DUALBOOT) \
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&& (defined(IAUDIO_X5) || defined(IAUDIO_M5))
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move.l (%a1), %d7 /* store GPIO_READ result for button check in main() */
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#endif
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clr.l (0x180,%a1) /* PLLCR = 0 */
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/* 64K DMA-capable SRAM at 0x10000000
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DMA is enabled and has priority in both banks
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10000e01,%d0
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movec.l %d0,%rambar1
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/* 32K Non-DMA SRAM at 0x10010000
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All types of accesses are allowed
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(We might want to restrict that to save power) */
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move.l #0x10010001,%d0
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movec.l %d0,%rambar0
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/* Chip select 0 - Flash ROM */
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moveq.l #0x00,%d0 /* CSAR0 - Base = 0x00000000 */
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move.l %d0,(0x080,%a0)
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move.l #FLASH_SIZE-0x10000+1,%d0 /* CSMR0 - All access */
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move.l %d0,(0x084,%a0)
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move.l #0x00000180,%d0 /* CSCR0 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x088,%a0)
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#if (defined MPIO_HD200) || (defined MPIO_HD300)
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/* Chip select 3 - LCD controller */
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move.l #0xf0000000,%d0 /* CSAR3 - Base = 0xf0000000 */
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move.l %d0,(0x0a4,%a0)
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moveq.l #0x1,%d0 /* CSMR3 - 64K */
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move.l %d0,(0x0a8,%a0)
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move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits no bursts */
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move.l %d0,(0x0ac,%a0)
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#elif !(defined IAUDIO_M3)
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/* Chip select 1 - LCD controller */
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move.l #0xf0000000,%d0 /* CSAR1 - Base = 0xf0000000 */
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move.l %d0,(0x08c,%a0)
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moveq.l #0x1,%d0 /* CSMR1 - 64K */
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move.l %d0,(0x090,%a0)
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move.l #0x00000180,%d0 /* CSCR1 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x094,%a0)
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#endif
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/* Chip select 2 - ATA controller */
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move.l #0x20000000,%d0 /* CSAR2 - Base = 0x20000000 */
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move.l %d0,(0x098,%a0)
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moveq.l #0x1,%d0 /* CSMR2 - 64K */
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move.l %d0,(0x09c,%a0)
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move.l #0x00000080,%d0 /* CSCR2 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x0a0,%a0) /* wait states are handled by the coldfire
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* IDE interface logic. */
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#if defined(CONFIG_USBOTG) && CONFIG_USBOTG == USBOTG_ISP1362
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/* Chip select 3 - USBOTG controller */
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move.l #0xc0000000,%d0 /* CSAR3 - Base = 0xc0000000 */
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move.l %d0,(0x0a4,%a0)
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moveq.l #0x1,%d0 /* CSMR3 - 64K */
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move.l %d0,(0x0a8,%a0)
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move.l #0x00000180,%d0 /* CSCR3 - no wait states, 16 bits, no bursts */
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move.l %d0,(0x0ac,%a0)
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#endif
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#ifdef BOOTLOADER
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/* Check if we have a Rockbox ROM image */
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lea 0x00100000,%a2
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move.l (%a2),%d0
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move.l #FLASH_MAGIC,%d1
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cmp.l %d0,%d1
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beq.b .imagefound
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/* Check for RAM image */
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lea 0x00001000,%a2
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move.l (%a2),%d0
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move.l #FLASH_MAGIC,%d1
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cmp.l %d0,%d1
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beq.b .imagefound
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/* Not either ROM or RAM image was found, so original firmware
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should be still present. */
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/* Check if the cookie is present. */
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lea 0x10017ffc,%a2
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move.l (%a2),%d0
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move.l #0xc0015a17,%d1
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cmp.l %d0,%d1
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bne.b .nocookie
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/* The cookie is not reset. This must mean that the boot loader
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has crashed. Let's start the original firmware immediately. */
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lea 0x10017ffc,%a2
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clr.l (%a2)
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jmp 8
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.nocookie:
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/* Set the cookie */
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move.l %d1,(%a2)
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.imagefound:
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/* Set up the DRAM controller. The refresh is based on the 11.2896MHz
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clock (5.6448MHz bus frequency). We haven't yet started the PLL */
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#if MEMORYSIZE < 32
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move.w #0x8004,%d0 /* DCR - Synchronous, 80 cycle refresh */
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#else
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move.w #0x8001,%d0 /* DCR - Synchronous, 32 cycle refresh */
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#endif
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move.w %d0,(0x100,%a0)
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/* Note on 32Mbyte models:
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We place the SDRAM on an 0x1000000 (16M) offset because
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the 5249 BGA chip has a fault which disables the use of A24. The
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suggested workaround by FreeScale is to offset the base address by
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half the DRAM size and increase the mask to the double.
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In our case this means that we set the base address 16M ahead and
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use a 64M mask.
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*/
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#if MEMORYSIZE < 32
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move.l #0x31002324,%d0 /* DACR0 - Base 0x31000000, Banks on 21 and up,
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CAS latency 2, Page mode, No refresh yet */
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move.l %d0,(0x108,%a0)
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move.l #0x00fc0001,%d0 /* Size: 16M */
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move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
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#else
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move.l #0x31002524,%d0 /* DACR0 - Base 0x31000000, Banks on 23 and up,
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CAS latency 2, Page mode, No refresh yet */
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move.l %d0,(0x108,%a0)
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move.l #0x03fc0001,%d0 /* Size: 64M because of workaround above */
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move.l %d0,(0x10c,%a0) /* DMR0 - 32Mb */
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#endif
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/* Precharge */
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moveq.l #8,%d0
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or.l %d0,(0x108,%a0) /* DACR0[IP] = 1, next access will issue a
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Precharge command */
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move.l #0xabcd1234,%d0
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move.l %d0,0x31000000 /* Issue precharge command */
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move.l #0x8000,%d0
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or.l %d0,(0x108,%a0) /* Enable refresh */
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/* Let it refresh */
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move.l #500,%d0
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.delayloop:
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subq.l #1,%d0
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bne.b .delayloop
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/* Mode Register init */
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moveq.l #0x40,%d0 /* DACR0[IMRS] = 1, next access will set the
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Mode Register */
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or.l %d0,(0x108,%a0)
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move.l #0xabcd1234,%d0
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move.l %d0,0x31000800 /* A11=1 means CASL=2 (connected to SDRAM A5). */
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/* DACR0[IMRS] gets deactivated by the SDRAM controller */
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/* Check if we have a Rockbox ROM image. For RAM image only cookie is
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not set at all. But we could support also RAM images loading. */
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lea 0x00100000,%a2
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move.l (%a2),%d0
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move.l #FLASH_MAGIC,%d1
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cmp.l %d0,%d1
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bne.b .noromimage
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/* Check again if the cookie is present. */
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lea 0x10017ffc,%a2
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move.l (%a2),%d0
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move.l #0xc0015a17,%d1
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cmp.l %d0,%d1
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bne.b .nocookie2
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/* We have found Rockbox in ROM!
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Clear the cookie and load the ROM image */
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lea 0x10017ffc,%a2
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clr.l (%a2)
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lea 0x00100028+4,%a2
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move.l (%a2),%sp
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lea 0x00100028+8,%a2
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move.l (%a2),%d0
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move.l %d0,%a2
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jmp (%a2)
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.nocookie2:
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/* Set the cookie */
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move.l %d1,(%a2)
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.noromimage:
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#endif /* BOOTLOADER */
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/* Invalicate cache */
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move.l #0x01000000,%d0
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movec.l %d0,%cacr
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/* Enable cache, default=non-cacheable, no buffered writes */
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move.l #0x80000000,%d0
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movec.l %d0,%cacr
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/* Cache enabled in SDRAM only, buffered writes enabled */
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move.l #0x3103c020,%d0
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movec.l %d0,%acr0
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/* Buffered writes enabled for the LCD */
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move.l #0xf000c060,%d0
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movec.l %d0,%acr1
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#ifndef BOOTLOADER
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/* .iram copy is done first since it is reclaimed for other
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* uninitialized sections */
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/* copy .init section */
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lea _initcopy,%a2
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lea _initstart,%a3
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lea _initend,%a4
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bra.b .initstart
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.initloop:
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move.l (%a2)+,(%a3)+
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.initstart:
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cmp.l %a3,%a4
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bhi.b .initloop
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/* copy the .iram section */
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lea _iramcopy,%a2
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lea _iramstart,%a3
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lea _iramend,%a4
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bra.b .iramstart
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.iramloop:
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move.l (%a2)+,(%a3)+
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.iramstart:
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cmp.l %a3,%a4
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bhi.b .iramloop
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/* zero out .ibss */
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lea _iedata,%a2
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lea _iend,%a4
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bra.b .iedatastart
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.iedataloop:
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clr.l (%a2)+
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.iedatastart:
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cmp.l %a2,%a4
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bhi.b .iedataloop
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#endif /* !BOOTLOADER */
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#ifdef IRIVER_H300_SERIES
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/* Set KEEP_ACT before doing the lengthy copy and zero-fill operations */
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move.l #0x00080000,%d0
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or.l %d0,(0xb4,%a1)
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or.l %d0,(0xb8,%a1)
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or.l %d0,(0xbc,%a1)
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#endif
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#if (defined MPIO_HD200) || (defined MPIO_HD300)
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/* Set KEEP_ACT
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* Set GPIO57 high to remove hissing nois on startup
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*/
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move.l #0x02200000,%d0
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or.l %d0,(0xb4,%a1)
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or.l %d0,(0xb8,%a1)
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or.l %d0,(0xbc,%a1)
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#endif
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/* zero out bss */
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lea _edata,%a2
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lea _end,%a4
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bra.b .edatastart
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.edataloop:
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clr.l (%a2)+
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.edatastart:
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cmp.l %a2,%a4
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bhi.b .edataloop
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/* copy the .data section */
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lea _datacopy,%a2
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lea _datastart,%a3
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cmp.l %a2,%a3
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beq.b .nodatacopy /* Don't copy if src and dest are equal */
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lea _dataend,%a4
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bra.b .datastart
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.dataloop:
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move.l (%a2)+,(%a3)+
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.datastart:
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cmp.l %a3,%a4
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bhi.b .dataloop
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.nodatacopy:
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/* Munge the main stack */
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lea stackbegin,%a2
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lea stackend,%a4
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move.l %a4,%sp
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move.l #0xdeadbeef,%d0
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.mungeloop:
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move.l %d0,(%a2)+
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cmp.l %a2,%a4
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bhi.b .mungeloop
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#if defined(BOOTLOADER) && (defined(IAUDIO_X5) || defined(IAUDIO_M5))
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move.l %d7, initial_gpio_read
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#endif
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jsr main
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.hoo:
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bra.b .hoo
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.section .resetvectors
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vectors:
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.long stackend
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.long start
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