amachronic b5558c1cf9 x1000: place SPL's NAND bounce buffers in DRAM ... This frees up 2 KiB in the SPL's memory map, leaving more room for code. Change-Id: I01bbe2ab2905b2773a8b76d8c53e9f3d55bd040f		2021-04-06 17:27:09 +01:00
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ingenic_jz47xx	Use STORAGE_NEEDS_BOUNCE_BUFFER instead of STORAGE_NEEDS_ALIGN	2021-03-27 15:02:18 -04:00
ingenic_x1000	x1000: place SPL's NAND bounce buffers in DRAM	2021-04-06 17:27:09 +01:00
mipsr2-endian.h	New port: FiiO M3K on bare metal	2021-03-28 00:01:37 +00:00
mmu-mips.c	New port: FiiO M3K on bare metal	2021-03-28 00:01:37 +00:00
mmu-mips.h	Move MIPS cache management functions to IRAM	2021-03-09 20:04:30 +00:00