fe23dc8f15
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13763 a1c6a512-1295-4272-9138-f99709370657
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2002 by Alan Korr
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* Copyright (C) 2007 by Michael Sevakis
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef SYSTEM_TARGET_H
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#define SYSTEM_TARGET_H
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#include "system-arm.h"
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#define inl(a) (*(volatile unsigned long *) (a))
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#define outl(a,b) (*(volatile unsigned long *) (b) = (a))
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#define inb(a) (*(volatile unsigned char *) (a))
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#define outb(a,b) (*(volatile unsigned char *) (b) = (a))
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#define inw(a) (*(volatile unsigned short *) (a))
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#define outw(a,b) (*(volatile unsigned short *) (b) = (a))
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extern unsigned int ipod_hw_rev;
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static inline void udelay(unsigned usecs)
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{
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unsigned stop = USEC_TIMER + usecs;
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while (TIME_BEFORE(USEC_TIMER, stop));
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}
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#ifdef CPU_PP502x
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static inline unsigned int current_core(void)
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{
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/*
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* PROCESSOR_ID seems to be 32-bits:
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* CPU = 0x55555555 = |01010101|01010101|01010101|01010101|
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* COP = 0xaaaaaaaa = |10101010|10101010|10101010|10101010|
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* ^
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*/
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unsigned int core;
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asm volatile (
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"mov %0, #0x60000000 \r\n" /* PROCESSOR_ID */
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"ldrb %0, [%0] \r\n" /* Just load the LSB */
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"mov %0, %0, lsr #7 \r\n" /* Bit 7 => index */
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: "=&r"(core) /* CPU=0, COP=1 */
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);
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return core;
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}
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#else
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unsigned int current_core(void);
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#endif
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#if CONFIG_CPU != PP5002
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#define HAVE_INVALIDATE_ICACHE
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static inline void invalidate_icache(void)
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{
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outl(inl(0xf000f044) | 0x6, 0xf000f044);
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while ((CACHE_CTL & 0x8000) != 0);
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}
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#define HAVE_FLUSH_ICACHE
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static inline void flush_icache(void)
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{
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outl(inl(0xf000f044) | 0x2, 0xf000f044);
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while ((CACHE_CTL & 0x8000) != 0);
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}
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#endif /* CONFIG_CPU */
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#endif /* SYSTEM_TARGET_H */
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