Jens Arnold
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fe23dc8f15
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Improved CPU clock setup for PP502x. PP5020 and PP5022 are not register compatible here, so define the PP5022 targets properly, and introduce a CPU_PP502x macro for easier family check. Improves stability on PP5020 (less freezing, tested with Mini G1) and reduces clock change penalty (500us on PP5020; uses the relock bit on PP5022).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13763 a1c6a512-1295-4272-9138-f99709370657
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2007-07-02 05:16:40 +00:00 |
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Michael Sevakis
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d803cf5e4e
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Heh. Better way to load the PROCESSOR_ID address. Thanks Thom. :)
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13156 a1c6a512-1295-4272-9138-f99709370657
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2007-04-14 11:46:05 +00:00 |
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Michael Sevakis
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036168cbf9
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PP5020/PP5024: Add ASM optimized inline current_core.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13155 a1c6a512-1295-4272-9138-f99709370657
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2007-04-14 11:15:43 +00:00 |
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Michael Sevakis
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20c6bf50fe
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Do the target shuffle again a better way by including from higher levels
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13151 a1c6a512-1295-4272-9138-f99709370657
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2007-04-14 01:18:06 +00:00 |
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Michael Sevakis
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d95c39072a
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Portal Player: Add invalidate_icache and flush_icache. Flush the cache on the core for newborn threads. In doing so, move more ARM stuff to the target tree and organize it to make a clean job of it. If anything isn't appropriate for some particular device give a hollar or even just fix it by some added #ifdefing. I was informed that the PP targets are register compatible so I'm going off that advice. The Sansa likes it though.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@13144 a1c6a512-1295-4272-9138-f99709370657
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2007-04-13 20:55:48 +00:00 |
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