e4bee2b109
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31229 a1c6a512-1295-4272-9138-f99709370657
438 lines
12 KiB
C
438 lines
12 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2009 by Michael Sparmann
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include "config.h"
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#include "usb.h"
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#include "usb-target.h"
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#include "usb_drv.h"
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#include "cpu.h"
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#include "system.h"
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#include "kernel.h"
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#include "panic.h"
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#include "usb-s3c6400x.h"
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#ifdef HAVE_USBSTACK
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#include "usb_ch9.h"
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#include "usb_core.h"
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#include <inttypes.h>
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#include "power.h"
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struct ep_type
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{
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bool active;
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bool busy;
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bool done;
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int rc;
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int size;
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struct semaphore complete;
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} ;
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static struct ep_type endpoints[USB_NUM_ENDPOINTS];
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/* USB control requests may be up to 64 bytes in size.
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Even though we never use anything more than the 8 header bytes,
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we are required to accept request packets of up to 64 bytes size.
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Provide buffer space for these additional payload bytes so that
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e.g. write descriptor requests (which are rejected by us, but the
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payload is transferred anyway) do not cause memory corruption.
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Fixes FS#12310. -- Michael Sparmann (theseven) */
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static struct
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{
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struct usb_ctrlrequest header; /* 8 bytes */
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unsigned char payload[64 - sizeof(struct usb_ctrlrequest)];
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} ctrlreq USB_DEVBSS_ATTR;
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int usb_drv_port_speed(void)
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{
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return (DSTS & 2) == 0 ? 1 : 0;
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}
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static void reset_endpoints(int reinit)
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{
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unsigned int i;
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for (i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
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{
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if (reinit) endpoints[i].active = false;
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endpoints[i].busy = false;
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endpoints[i].rc = -1;
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endpoints[i].done = true;
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semaphore_release(&endpoints[i].complete);
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}
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DEPCTL(0, false) = DEPCTL_usbactep | (1 << DEPCTL_nextep_bitp);
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DEPCTL(0, true) = DEPCTL_usbactep;
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DEPTSIZ(0, true) = (1 << DEPTSIZ_pkcnt_bitp) | (1 << DEPTSIZ0_supcnt_bitp) | 64;
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DEPDMA(0, true) = &ctrlreq;
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DEPCTL(0, true) |= DEPCTL_epena | DEPCTL_cnak;
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if (reinit)
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{
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/* The size is getting set to zero, because we don't know
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whether we are Full Speed or High Speed at this stage */
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DEPCTL(1, false) = DEPCTL_setd0pid | (3 << DEPCTL_nextep_bitp);
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DEPCTL(2, true) = DEPCTL_setd0pid;
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DEPCTL(3, false) = DEPCTL_setd0pid | (0 << DEPCTL_nextep_bitp);
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DEPCTL(4, true) = DEPCTL_setd0pid;
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}
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else
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{
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DEPCTL(1, false) = (DEPCTL(1, false) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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DEPCTL(2, true) = (DEPCTL(2, true) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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DEPCTL(3, false) = (DEPCTL(3, false) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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DEPCTL(4, true) = (DEPCTL(4, true) & ~DEPCTL_usbactep) | DEPCTL_setd0pid;
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}
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DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all EPs */
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}
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int usb_drv_request_endpoint(int type, int dir)
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{
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for(size_t ep = (dir == USB_DIR_IN) ? 1 : 2; ep < USB_NUM_ENDPOINTS; ep += 2)
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if (!endpoints[ep].active)
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{
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endpoints[ep].active = true;
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DEPCTL(ep, !dir) = (DEPCTL(ep, !dir) & ~(DEPCTL_eptype_bits << DEPCTL_eptype_bitp)) |
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(type << DEPCTL_eptype_bitp) | DEPCTL_epena;
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return ep | dir;
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}
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return -1;
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}
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void usb_drv_release_endpoint(int ep)
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{
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ep = ep & 0x7f;
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if (ep < 1 || ep > USB_NUM_ENDPOINTS)
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return;
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endpoints[ep].active = false;
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}
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static void usb_reset(void)
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{
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DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
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OPHYPWR = 0; /* PHY: Power up */
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udelay(10);
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OPHYUNK1 = 1;
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OPHYUNK2 = 0xE3F;
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ORSTCON = 1; /* PHY: Assert Software Reset */
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udelay(10);
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ORSTCON = 0; /* PHY: Deassert Software Reset */
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OPHYUNK3 = 0x600;
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OPHYCLK = SYNOPSYSOTG_CLOCK;
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udelay(400);
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GRSTCTL = GRSTCTL_csftrst; /* OTG: Assert Software Reset */
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while (GRSTCTL & GRSTCTL_csftrst); /* Wait for OTG to ack reset */
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while (!(GRSTCTL & GRSTCTL_ahbidle)); /* Wait for OTG AHB master idle */
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GRXFSIZ = 512;
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GNPTXFSIZ = MAKE_FIFOSIZE_DATA(512);
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GAHBCFG = SYNOPSYSOTG_AHBCFG;
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GUSBCFG = (1 << 12) | (1 << 10) | GUSBCFG_phy_if; /* OTG: 16bit PHY and some reserved bits */
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DCFG = DCFG_nzstsouthshk; /* Address 0 */
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DCTL = DCTL_pwronprgdone; /* Soft Reconnect */
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DIEPMSK = DIEPINT_timeout | DIEPINT_ahberr | DIEPINT_xfercompl;
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DOEPMSK = DIEPINT_timeout | DIEPINT_ahberr | DIEPINT_xfercompl;
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DAINTMSK = 0xFFFFFFFF; /* Enable interrupts on all endpoints */
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GINTMSK = GINTMSK_outepintr | GINTMSK_inepintr | GINTMSK_usbreset | GINTMSK_enumdone;
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reset_endpoints(1);
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}
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static void handle_ep_int(int out)
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{
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static const uint8_t eps[2][3] = { /* IN */ {0, 1, 3}, /* OUT */ {0, 2, 4}};
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for (int i = 0, ep = eps[!!out][i]; i < 3; ep = eps[!!out][i])
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{
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uint32_t epints = DEPINT(ep, out);
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if (!epints)
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continue;
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if (epints & DIEPINT_xfercompl)
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{
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invalidate_dcache();
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int bytes = endpoints[ep].size - (DEPTSIZ(ep, out) & (DEPTSIZ_xfersize_bits < DEPTSIZ_xfersize_bitp));
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if (endpoints[ep].busy)
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{
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endpoints[ep].busy = false;
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endpoints[ep].rc = 0;
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endpoints[ep].done = true;
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usb_core_transfer_complete(ep, out ? USB_DIR_OUT : USB_DIR_IN, 0, bytes);
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semaphore_release(&endpoints[ep].complete);
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}
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}
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if (epints & DIEPINT_ahberr)
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panicf("USB: AHB error on EP%d (dir %d)", ep, out);
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if (epints & DIEPINT_timeout)
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{
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if (!out)
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{
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if (endpoints[i].busy)
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{
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endpoints[i].busy = false;
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endpoints[i].rc = 1;
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endpoints[i].done = true;
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semaphore_release(&endpoints[i].complete);
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}
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}
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else
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{ /* SETUP phase done */
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invalidate_dcache();
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if (ep == 0)
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{
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if (ctrlreq.header.bRequest == 5)
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{
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/* Already set the new address here,
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before passing the packet to the core.
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See below (usb_drv_set_address) for details. */
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DCFG = (DCFG & ~(DCFG_devadr_bits << DCFG_devadr_bitp)) | (ctrlreq.header.wValue << DCFG_devadr_bitp);
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}
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usb_core_control_request(&ctrlreq.header);
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}
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else panicf("USB: SETUP done on OUT EP%d!?", ep);
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}
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}
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/* Make sure EP0 OUT is set up to accept the next request */
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if (out && ep == 0)
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{
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DEPTSIZ(0, true) = (1 << DEPTSIZ0_supcnt_bitp) | (1 << DEPTSIZ0_pkcnt_bitp) | 64;
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DEPDMA(0, true) = &ctrlreq;
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DEPCTL(0, true) |= DEPCTL_epena | DEPCTL_cnak;
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}
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DEPINT(ep, true) = epints;
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}
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}
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/* IRQ handler */
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void INT_USB_FUNC(void)
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{
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uint32_t ints = GINTSTS;
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if (ints & GINTMSK_usbreset)
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{
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DCFG = DCFG_nzstsouthshk; /* Address 0 */
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reset_endpoints(1);
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usb_core_bus_reset();
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}
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if (ints & GINTMSK_enumdone) /* enumeration done, we now know the speed */
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{
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/* Set up the maximum packet sizes accordingly */
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uint32_t maxpacket = (usb_drv_port_speed() ? 512 : 64) << DEPCTL_mps_bitp;
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DEPCTL(1, false) = (DEPCTL(1, false) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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DEPCTL(2, true) = (DEPCTL(2, true) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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DEPCTL(3, false) = (DEPCTL(3, false) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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DEPCTL(4, true) = (DEPCTL(4, true) & ~(DEPCTL_mps_bits << DEPCTL_mps_bitp)) | maxpacket;
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}
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if (ints & GINTMSK_inepintr)
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handle_ep_int(false);
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if (ints & GINTMSK_outepintr)
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handle_ep_int(true);
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GINTSTS = ints;
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}
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void usb_drv_set_address(int address)
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{
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(void)address;
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/* Ignored intentionally, because the controller requires us to set the
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new address before sending the response for some reason. So we'll
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already set it when the control request arrives, before passing that
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into the USB core, which will then call this dummy function. */
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}
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static void ep_transfer(int ep, void *ptr, int length, int out)
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{
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endpoints[ep].busy = true;
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endpoints[ep].size = length;
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if (out)
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DEPCTL(ep, out) &= ~DEPCTL_naksts;
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DEPCTL(ep, out) |= DEPCTL_usbactep;
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int blocksize = usb_drv_port_speed() ? 512 : 64;
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int packets = (length + blocksize - 1) / blocksize;
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if (packets == 0)
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packets = 1;
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DEPTSIZ(ep, out) = length | (packets << DEPTSIZ0_pkcnt_bitp);
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DEPDMA(ep, out) = length ? ptr : NULL;
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clean_dcache();
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DEPCTL(ep, out) |= DEPCTL_epena | DEPCTL_cnak;
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}
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int usb_drv_send(int endpoint, void *ptr, int length)
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{
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endpoint = EP_NUM(endpoint);
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endpoints[endpoint].done = false;
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ep_transfer(endpoint, ptr, length, false);
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while (!endpoints[endpoint].done && endpoints[endpoint].busy)
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semaphore_wait(&endpoints[endpoint].complete, TIMEOUT_BLOCK);
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return endpoints[endpoint].rc;
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}
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int usb_drv_send_nonblocking(int endpoint, void *ptr, int length)
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{
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ep_transfer(EP_NUM(endpoint), ptr, length, false);
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return 0;
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}
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int usb_drv_recv(int endpoint, void* ptr, int length)
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{
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ep_transfer(EP_NUM(endpoint), ptr, length, true);
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return 0;
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}
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void usb_drv_cancel_all_transfers(void)
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{
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int flags = disable_irq_save();
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reset_endpoints(0);
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restore_irq(flags);
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}
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void usb_drv_set_test_mode(int mode)
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{
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(void)mode;
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}
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bool usb_drv_stalled(int endpoint, bool in)
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{
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return DEPCTL(endpoint, !in) & DEPCTL_naksts;
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}
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void usb_drv_stall(int endpoint, bool stall, bool in)
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{
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if (stall)
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DEPCTL(endpoint, !in) |= DEPCTL_naksts;
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else
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DEPCTL(endpoint, !in) &= ~DEPCTL_naksts;
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}
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void usb_drv_init(void)
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{
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/* Enable USB clock */
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#if CONFIG_CPU==S5L8701
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PWRCON &= ~0x4000;
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PWRCONEXT &= ~0x800;
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INTMSK |= INTMSK_USB_OTG;
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#elif CONFIG_CPU==S5L8702
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PWRCON(0) &= ~0x4;
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PWRCON(1) &= ~0x8;
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VIC0INTENABLE |= 1 << 19;
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#endif
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PCGCCTL = 0;
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/* reset the beast */
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usb_reset();
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}
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void usb_drv_exit(void)
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{
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DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
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OPHYPWR = 0xF; /* PHY: Power down */
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udelay(10);
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ORSTCON = 7; /* Put the PHY into reset (needed to get current down) */
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udelay(10);
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PCGCCTL = 1; /* Shut down PHY clock */
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#if CONFIG_CPU==S5L8701
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PWRCON |= 0x4000;
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PWRCONEXT |= 0x800;
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#elif CONFIG_CPU==S5L8702
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PWRCON(0) |= 0x4;
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PWRCON(1) |= 0x8;
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#endif
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}
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void usb_init_device(void)
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{
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for (unsigned i = 0; i < sizeof(endpoints)/sizeof(struct ep_type); i++)
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semaphore_init(&endpoints[i].complete, 1, 0);
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/* Power up the core clocks to allow writing
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to some registers needed to power it down */
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PCGCCTL = 0;
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#if CONFIG_CPU==S5L8701
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PWRCON &= ~0x4000;
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PWRCONEXT &= ~0x800;
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INTMSK |= INTMSK_USB_OTG;
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#elif CONFIG_CPU==S5L8702
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PWRCON(0) &= ~0x4;
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PWRCON(1) &= ~0x8;
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VIC0INTENABLE |= 1 << 19;
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#endif
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usb_drv_exit();
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}
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void usb_enable(bool on)
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{
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if (on) usb_core_init();
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else usb_core_exit();
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}
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void usb_attach(void)
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{
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usb_enable(true);
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}
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int usb_detect(void)
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{
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if (charger_inserted())
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return USB_INSERTED;
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return USB_EXTRACTED;
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}
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#else
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void usb_init_device(void)
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{
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DCTL = DCTL_pwronprgdone | DCTL_sftdiscon;
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ORSTCON = 1; /* Put the PHY into reset (needed to get current down) */
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PCGCCTL = 1; /* Shut down PHY clock */
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OPHYPWR = 0xF; /* PHY: Power down */
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#if CONFIG_CPU==S5L8701
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PWRCON |= 0x4000;
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PWRCONEXT |= 0x800;
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#elif CONFIG_CPU==S5L8702
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PWRCON(0) |= 0x4;
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PWRCON(1) |= 0x8;
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#endif
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}
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void usb_enable(bool on)
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{
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(void)on;
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}
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/* Always return false for now */
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int usb_detect(void)
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{
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return USB_EXTRACTED;
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}
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#endif
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