c7b698119d
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@21007 a1c6a512-1295-4272-9138-f99709370657
72 lines
2.7 KiB
C
72 lines
2.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright © 2008 Rafaël Carré
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef CLOCK_TARGET_H
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#define CLOCK_TARGET_H
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/* returns clock divider, given maximal target frequency and clock reference */
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#define CLK_DIV(ref, target) ((ref + target - 1) / target)
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/* PLL */
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#define AS3525_PLLA_FREQ 248000000
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#define AS3525_PLLA_SETTING 0x261F
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/* CPU */
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/* ensure that PLLA_FREQ * prediv == CPUFREQ_MAX */
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#define AS3525_CPU_PREDIV 0 /* div = 1/1 */
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#define CPUFREQ_MAX 248000000
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#define CPUFREQ_DEFAULT 24800000
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#define CPUFREQ_NORMAL 31000000
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/* peripherals */
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#define AS3525_PCLK_FREQ 62000000
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#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_PCLK_FREQ) - 1) >= (1<<4) /* 4 bits */
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#error PCLK frequency is too low : clock divider will not fit !
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#endif
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#define AS3525_IDE_FREQ 90000000 /* The OF uses 66MHz maximal freq
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but sd transfers fail on some
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players with this limit */
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#if (CLK_DIV(AS3525_PLLA_FREQ, AS3525_IDE_FREQ) - 1) >= (1<<4) /* 4 bits */
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#error IDE frequency is too low : clock divider will not fit !
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#endif
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#define AS3525_I2C_FREQ 400000
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#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_I2C_FREQ)) >= (1<<10) /* 2+8 bits */
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#error I2C frequency is too low : clock divider will not fit !
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#endif
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#define AS3525_DBOP_FREQ 32000000
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#if (CLK_DIV(AS3525_PCLK_FREQ, AS3525_DBOP_FREQ) - 1) >= (1<<3) /* 3 bits */
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#error DBOP frequency is too low : clock divider will not fit !
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#endif
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#define AS3525_SD_IDENT_FREQ 400000 /* must be between 100 & 400 kHz */
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#if ((CLK_DIV(AS3525_PCLK_FREQ, AS3525_SD_IDENT_FREQ) / 2) - 1) >= (1<<8) /* 8 bits */
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#error SD IDENTIFICATION frequency is too low : clock divider will not fit !
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#endif
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#endif /* CLOCK_TARGET_H */
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