i2c clock frequency uses pclk as reference, not plla
i2c clock divider is only 10 bits, not 16
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20929 a1c6a512-1295-4272-9138-f99709370657
Inline the 2 uses, and use a preprocessor sanity check for identification frequency
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20924 a1c6a512-1295-4272-9138-f99709370657
Fix CGU_DBOP setting
Set PCLK to the exact frequency (62MHz, not the maximal frequency)
Use a better comment for CLK_DIV macro
Use preprocessor safety checks for clock divider sizes to avoid future mistakes (not for SD_IDENT frequency since that check is handled by mci_set_clock_divider)
Use maximal IDE frequency of 66MHz (like OF), not 90MHz like written in AS3525 datasheet. The IDE chip is somehow linked to internal storage, and a too high frequency could affect the storage driver.
Use the same DBOP frequency of 32MHz for all models (like OF, verified clip, fuze, e200v2 and m200v4), compromise between performance and battery life could be added in the future for each target
Performance increase on Sansa Fuze with DBOP freq. set to 64MHz: +12% fps for lcd_update, +1% fps for yuv
Thanks to daytona955 on the forums for his help
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@20923 a1c6a512-1295-4272-9138-f99709370657
Reorder system_init() to initialize peripherals not only in bootloader
Use a 65MHz PCLK (and memclk) which will be needed for realtime decoding
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@19330 a1c6a512-1295-4272-9138-f99709370657
