47cbeb2e67
Many SPI NAND flash chips have on-die ECC engines that report ECC status via the status feature register. This code handles the common case where ECC status is reported with 2 bits: one bit to indicate if flips were detected & corrected, and another bit to indicate an uncorrectable error. Change-Id: I5d587cd960ca9d090d2629e890724a6bc411e70c |
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ingenic_jz47xx | ||
ingenic_x1000 | ||
mipsr2-endian.h | ||
mmu-mips.c | ||
mmu-mips.h |