28dec004c0
* Add wildcards to various sections placements a la *(".text") => "*(.text*)"
* Remove hacky bits from those linker scripts (no problem encountered testing)
* Change section for asm functions from .<section> to .<section>.<function>
so that -ffunction-sections works for those asm file too.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@31337 a1c6a512-1295-4272-9138-f99709370657
115 lines
2.3 KiB
Text
115 lines
2.3 KiB
Text
#include "config.h"
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#include "imx31l.h"
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ENTRY(start)
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OUTPUT_FORMAT(elf32-littlearm)
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OUTPUT_ARCH(arm)
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STARTUP(target/arm/imx31/crt0.o)
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#define DRAMSIZE (1 << 20) /* Limit 1 MB for bootloader */
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#define DRAMORIG 0x02000000
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/* #define IRAMORIG 0x1FFFC000 */
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#define IRAM DRAM
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#define IRAMSIZE IRAM_SIZE
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#define IRAMORIG DRAMORIG
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#define FLASHORIG 0x0000000
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#define FLASHSIZE 1M
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MEMORY
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{
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DRAM : ORIGIN = DRAMORIG, LENGTH = DRAMSIZE
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QHARRAY : ORIGIN = QHARRAY_PHYS_ADDR, LENGTH = QHARRAY_SIZE
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}
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SECTIONS
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{
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. = DRAMORIG;
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.text :
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{
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*(.init.text)
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*(.text*)
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*(.icode*)
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*(.glue_7)
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*(.glue_7t)
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. = ALIGN(0x4);
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} > DRAM
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.rodata :
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{
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*(.rodata*)
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*(.irodata*)
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. = ALIGN(0x4);
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/* Pseudo-allocate the copies of the data sections */
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_datacopy = .;
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} > DRAM
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.data :
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{
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*(.data*)
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*(.idata*)
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_dataend = . ;
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} > DRAM
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#if 0 /* Unneeded at the moment */
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/* .ncdata section is placed at uncached physical alias address and is
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* loaded at the proper cached virtual address - no copying is
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* performed in the init code */
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.ncdata . + NOCACHE_BASE :
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{
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. = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
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*(.ncdata*)
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. = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
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} AT> DRAM
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#endif
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.vectors 0x0 :
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{
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_vectorsstart = .;
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*(.vectors);
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KEEP(*(.vectors));
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_vectorsend = .;
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} AT > DRAM
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_vectorscopy = LOADADDR(.vectors);
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.stack (NOLOAD) :
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{
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*(.stack)
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_stackbegin = .;
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stackbegin = .;
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. += 0x2000;
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_stackend = .;
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stackend = .;
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} > IRAM
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/* .bss and .ncbss are treated as a single section to use one init loop to
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* zero it - note "_edata" and "_end" */
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.bss (NOLOAD) :
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{
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_edata = .;
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*(.bss*);
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*(.ibss*);
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*(COMMON)
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. = ALIGN(0x4);
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} > DRAM
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.ncbss . + NOCACHE_BASE (NOLOAD) :
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{
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. = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
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*(.ncbss*)
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. = ALIGN(CACHEALIGN_SIZE); /* >= Cache line boundary */
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} AT> DRAM
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.endaddr . - NOCACHE_BASE (NOLOAD) :
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{
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_end = .;
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} > DRAM
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.qharray (NOLOAD) :
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{
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_qharray = .;
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*(.qharray)
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_qharrayend = .;
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} > QHARRAY
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}
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