98246b82b9
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29113 a1c6a512-1295-4272-9138-f99709370657
152 lines
5.5 KiB
C
152 lines
5.5 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2010 by Michael Sevakis
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*
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* i.MX31 DVFS and DPTC driver declarations
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef _DVFS_DPTC_IMX31_H_
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#define _DVFS_DPTC_IMX31_H_
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/* DVFS load tracking signals */
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enum DVFS_LT_SIGS
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{
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DVFS_LT_SIG_M3IF_M0_BUF = 0, /* Hready signal of M3IF's master #0
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(L2 Cache) */
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DVFS_LT_SIG_M3IF_M1 = 1, /* Hready signal of M3IF's master #1
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(L2 Cache) */
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DVFS_LT_SIG_MBX_MBXCLKGATE = 2, /* Hready signal of M3IF's master #2
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(MBX) */
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DVFS_LT_SIG_M3IF_M3 = 3, /* Hready signal of M3IF's master #3
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(MAX) */
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DVFS_LT_SIG_M3IF_M4 = 4, /* Hready signal of M3IF's master #4
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(SDMA) */
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DVFS_LT_SIG_M3IF_M5 = 5, /* Hready signal of M3IF's master #5
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(mpeg4_vga_encoder) */
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DVFS_LT_SIG_M3IF_M6 = 6, /* Hready signal of M3IF's master #6
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(IPU) */
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DVFS_LT_SIG_M3IF_M7 = 7, /* Hready signal of M3IF's master #7
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(IPU) */
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DVFS_LT_SIG_ARM11_P_IRQ_B_RBT_GATE = 8, /* ARM normal interrupt */
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DVFS_LT_SIG_ARM11_P_FIQ_B_RBT_GATE = 9, /* ARM fast interrupt */
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DVFS_LT_SIG_IPI_GPIO1_INT0 = 10, /* Interrupt line from GPIO */
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DVFS_LT_SIG_IPI_INT_IPU_FUNC = 11, /* Interrupt line from IPU */
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DVFS_LT_SIG_DVGP0 = 12, /* Software-controllable general-purpose
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bits from the CCM */
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DVFS_LT_SIG_DVGP1 = 13, /* Software-controllable general-purpose
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bits from the CCM */
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DVFS_LT_SIG_DVGP2 = 14, /* Software-controllable general-purpose
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bits from the CCM */
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DVFS_LT_SIG_DVGP3 = 15, /* Software-controllable general-purpose
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bits from the CCM */
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};
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enum DVFS_DVGPS
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{
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DVFS_DVGP_0 = 0,
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DVFS_DVGP_1,
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DVFS_DVGP_2,
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DVFS_DVGP_3,
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};
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union dvfs_dptc_voltage_table_entry
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{
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uint8_t sw[4]; /* Access as array */
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struct
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{
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/* Chosen by PMIC pin states */
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/* when SWxABDVS bit is 1: */
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/* DVSSWxA DVSSWxB */
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uint8_t sw1a; /* 0 0 */
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uint8_t sw1advs; /* 1 0 */
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uint8_t sw1bdvs; /* 0 1 */
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uint8_t sw1bstby; /* 1 1 */
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};
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};
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struct dptc_dcvr_table_entry
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{
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uint32_t dcvr0; /* DCVR register values for working point */
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uint32_t dcvr1;
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uint32_t dcvr2;
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uint32_t dcvr3;
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};
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struct dvfs_clock_table_entry
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{
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uint32_t pll_val; /* Setting for target PLL */
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uint32_t pdr_val; /* Post-divider for target setting */
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uint32_t pll_num : 1; /* 1 = MCU PLL, 0 = Serial PLL */
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uint32_t vscnt : 3; /* Voltage scaling counter, CKIL delay */
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};
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struct dvfs_lt_signal_descriptor
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{
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uint8_t weight : 3; /* Signal weight = 0-7 */
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uint8_t detect : 1; /* 1 = edge-detected */
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};
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#define DVFS_NUM_LEVELS 4
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#define DPTC_NUM_WP 17
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/* 0 and 3 are *required*. DVFS hardware depends upon DVSUP pins showing
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* minimum (11) and maximum (00) levels or interrupts will be continuously
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* asserted. */
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#define DVFS_LEVEL_0 (1u << 0)
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#define DVFS_LEVEL_1 (1u << 1)
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#define DVFS_LEVEL_2 (1u << 2)
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#define DVFS_LEVEL_3 (1u << 3)
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extern long cpu_voltage_setting;
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void dvfs_dptc_init(void);
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void dvfs_dptc_start(void);
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void dvfs_dptc_stop(void);
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void dvfs_start(void);
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void dvfs_stop(void);
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bool dvfs_enabled(void);
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void dvfs_wfi_monitor(bool on);
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void dvfs_set_lt_weight(enum DVFS_LT_SIGS index, unsigned long value);
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unsigned long dvfs_get_lt_weight(enum DVFS_LT_SIGS index);
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void dvfs_set_lt_detect(enum DVFS_LT_SIGS index, bool edge);
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bool dvfs_get_lt_detect(enum DVFS_LT_SIGS index);
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void dvfs_set_gp_bit(enum DVFS_DVGPS dvgp, bool assert);
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bool dvfs_get_gp_bit(enum DVFS_DVGPS dvgp);
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void dvfs_int_mask(bool mask);
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void dvfs_set_gp_sense(int level_code, unsigned long detect_mask);
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void dvfs_get_gp_sense(int *level_code, unsigned long *detect_mask);
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unsigned int dvfs_level_mask(void);
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unsigned int dvfs_dptc_get_voltage(void);
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unsigned int dvfs_get_level(void);
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void dvfs_set_level(unsigned int level);
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void dptc_start(void);
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void dptc_stop(void);
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bool dptc_enabled(void);
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unsigned int dptc_get_wp(void);
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void dptc_set_wp(unsigned int wp);
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#endif /* _DVFS_DPTC_IMX31_H_ */
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