191320cd0f
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17683 a1c6a512-1295-4272-9138-f99709370657
326 lines
8.7 KiB
C
326 lines
8.7 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* $Id$
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*
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* Copyright (C) 2005 Jens Arnold
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*
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* All files in this archive are subject to the GNU General Public License.
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* See the file COPYING in the source tree root for full license agreement.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#include <stdbool.h>
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#include "config.h"
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#include "cpu.h"
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#include "system.h"
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#include "timer.h"
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#include "logf.h"
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static int timer_prio = -1;
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void SHAREDBSS_ATTR (*pfn_timer)(void) = NULL; /* timer callback */
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void SHAREDBSS_ATTR (*pfn_unregister)(void) = NULL; /* unregister callback */
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#ifdef CPU_COLDFIRE
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static int base_prescale;
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#elif defined CPU_PP || CONFIG_CPU == PNX0101
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static long SHAREDBSS_ATTR cycles_new = 0;
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#endif
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/* interrupt handler */
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#if CONFIG_CPU == SH7034
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void IMIA4(void) __attribute__((interrupt_handler));
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void IMIA4(void)
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{
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if (pfn_timer != NULL)
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pfn_timer();
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and_b(~0x01, &TSR4); /* clear the interrupt */
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}
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#elif defined CPU_COLDFIRE
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void TIMER1(void) __attribute__ ((interrupt_handler));
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void TIMER1(void)
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{
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if (pfn_timer != NULL)
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pfn_timer();
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TER1 = 0xff; /* clear all events */
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}
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#elif defined(CPU_PP)
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void TIMER2(void)
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{
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TIMER2_VAL; /* ACK interrupt */
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if (cycles_new > 0)
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{
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TIMER2_CFG = 0xc0000000 | (cycles_new - 1);
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cycles_new = 0;
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}
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if (pfn_timer != NULL)
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{
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cycles_new = -1;
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/* "lock" the variable, in case timer_set_period()
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* is called within pfn_timer() */
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pfn_timer();
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cycles_new = 0;
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}
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}
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#elif CONFIG_CPU == PNX0101
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void TIMER1_ISR(void)
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{
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if (cycles_new > 0)
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{
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TIMER1.load = cycles_new - 1;
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cycles_new = 0;
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}
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if (pfn_timer != NULL)
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{
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cycles_new = -1;
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/* "lock" the variable, in case timer_set_period()
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* is called within pfn_timer() */
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pfn_timer();
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cycles_new = 0;
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}
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TIMER1.clr = 1; /* clear the interrupt */
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}
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#endif /* CONFIG_CPU */
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static bool timer_set(long cycles, bool start)
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{
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#if (CONFIG_CPU == SH7034) || defined(CPU_COLDFIRE)
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int phi = 0; /* bits for the prescaler */
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int prescale = 1;
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while (cycles > 0x10000)
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{ /* work out the smallest prescaler that makes it fit */
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#if CONFIG_CPU == SH7034
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phi++;
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#endif
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prescale *= 2;
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cycles >>= 1;
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}
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#endif
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#if CONFIG_CPU == PNX0101
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if (start)
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{
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if (pfn_unregister != NULL)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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TIMER1.ctrl &= ~0x80; /* disable the counter */
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TIMER1.ctrl |= 0x40; /* reload after counting down to zero */
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TIMER1.ctrl &= ~0xc; /* no prescaler */
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TIMER1.clr = 1; /* clear an interrupt event */
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}
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if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
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{ /* enable timer */
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TIMER1.load = cycles - 1;
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TIMER1.ctrl |= 0x80; /* enable the counter */
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}
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else
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cycles_new = cycles;
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return true;
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#elif CONFIG_CPU == SH7034
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if (prescale > 8)
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return false;
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if (start)
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{
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if (pfn_unregister != NULL)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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and_b(~0x10, &TSTR); /* Stop the timer 4 */
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and_b(~0x10, &TSNC); /* No synchronization */
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and_b(~0x10, &TMDR); /* Operate normally */
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TIER4 = 0xF9; /* Enable GRA match interrupt */
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}
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TCR4 = 0x20 | phi; /* clear at GRA match, set prescaler */
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GRA4 = (unsigned short)(cycles - 1);
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if (start || (TCNT4 >= GRA4))
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TCNT4 = 0;
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and_b(~0x01, &TSR4); /* clear an eventual interrupt */
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return true;
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#elif defined CPU_COLDFIRE
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if (prescale > 4096/CPUFREQ_MAX_MULT)
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return false;
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if (prescale > 256/CPUFREQ_MAX_MULT)
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{
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phi = 0x05; /* prescale sysclk/16, timer enabled */
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prescale >>= 4;
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}
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else
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phi = 0x03; /* prescale sysclk, timer enabled */
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base_prescale = prescale;
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prescale *= (cpu_frequency / CPU_FREQ);
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if (start)
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{
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if (pfn_unregister != NULL)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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phi &= ~1; /* timer disabled at start */
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/* If it is already enabled, writing a 0 to the RST bit will clear
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the register, so we clear RST explicitly before writing the real
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data. */
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TMR1 = 0;
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}
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/* We are using timer 1 */
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TMR1 = 0x0018 | (unsigned short)phi | ((unsigned short)(prescale - 1) << 8);
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TRR1 = (unsigned short)(cycles - 1);
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if (start || (TCN1 >= TRR1))
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TCN1 = 0; /* reset the timer */
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TER1 = 0xff; /* clear all events */
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return true;
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#elif defined(CPU_PP)
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if (cycles > 0x20000000 || cycles < 2)
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return false;
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if (start)
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{
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if (pfn_unregister != NULL)
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{
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pfn_unregister();
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pfn_unregister = NULL;
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}
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CPU_INT_DIS = TIMER2_MASK;
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COP_INT_DIS = TIMER2_MASK;
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}
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if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
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TIMER2_CFG = 0xc0000000 | (cycles - 1); /* enable timer */
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else
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cycles_new = cycles;
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return true;
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#elif (CONFIG_CPU == IMX31L)
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/* TODO */
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(void)cycles; (void)start;
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return false;
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#else
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return __TIMER_SET(cycles, start);
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#endif /* CONFIG_CPU */
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}
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#ifdef CPU_COLDFIRE
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void timers_adjust_prescale(int multiplier, bool enable_irq)
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{
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/* tick timer */
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TMR0 = (TMR0 & 0x00ef)
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| ((unsigned short)(multiplier - 1) << 8)
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| (enable_irq ? 0x10 : 0);
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if (pfn_timer)
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{
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/* user timer */
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int prescale = base_prescale * multiplier;
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TMR1 = (TMR1 & 0x00ef)
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| ((unsigned short)(prescale - 1) << 8)
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| (enable_irq ? 0x10 : 0);
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}
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}
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#endif
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/* Register a user timer, called every <cycles> TIMER_FREQ cycles */
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bool timer_register(int reg_prio, void (*unregister_callback)(void),
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long cycles, int int_prio, void (*timer_callback)(void)
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IF_COP(, int core))
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{
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if (reg_prio <= timer_prio || cycles == 0)
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return false;
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#if CONFIG_CPU == SH7034
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if (int_prio < 1 || int_prio > 15)
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return false;
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#endif
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if (!timer_set(cycles, true))
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return false;
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pfn_timer = timer_callback;
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pfn_unregister = unregister_callback;
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timer_prio = reg_prio;
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#if CONFIG_CPU == SH7034
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IPRD = (IPRD & 0xFF0F) | int_prio << 4; /* interrupt priority */
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or_b(0x10, &TSTR); /* start timer 4 */
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return true;
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#elif defined CPU_COLDFIRE
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ICR2 = 0x90; /* interrupt on level 4.0 */
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and_l(~(1<<10), &IMR);
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TMR1 |= 1; /* start timer */
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return true;
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#elif defined(CPU_PP)
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/* unmask interrupt source */
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#if NUM_CORES > 1
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if (core == COP)
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COP_INT_EN = TIMER2_MASK;
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else
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#endif
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CPU_INT_EN = TIMER2_MASK;
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return true;
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#elif CONFIG_CPU == PNX0101
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irq_set_int_handler(IRQ_TIMER1, TIMER1_ISR);
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irq_enable_int(IRQ_TIMER1);
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return true;
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#elif CONFIG_CPU == IMX31L
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/* TODO */
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return false;
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#else
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return __TIMER_REGISTER(reg_prio, unregister_callback, cycles,
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int_prio, timer_callback);
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#endif
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/* Cover for targets that don't use all these */
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(void)reg_prio;
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(void)unregister_callback;
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(void)cycles;
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/* TODO: Implement for PortalPlayer and iFP (if possible) */
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(void)int_prio;
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(void)timer_callback;
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}
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bool timer_set_period(long cycles)
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{
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return timer_set(cycles, false);
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}
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void timer_unregister(void)
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{
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#if CONFIG_CPU == SH7034
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and_b(~0x10, &TSTR); /* stop the timer 4 */
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IPRD = (IPRD & 0xFF0F); /* disable interrupt */
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#elif defined CPU_COLDFIRE
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TMR1 = 0; /* disable timer 1 */
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or_l((1<<10), &IMR); /* disable interrupt */
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#elif defined(CPU_PP)
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TIMER2_CFG = 0; /* stop timer 2 */
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CPU_INT_DIS = TIMER2_MASK;
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COP_INT_DIS = TIMER2_MASK;
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#elif CONFIG_CPU == PNX0101
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TIMER1.ctrl &= ~0x80; /* disable timer 1 */
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irq_disable_int(IRQ_TIMER1);
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#elif CONFIG_CPU == S3C2440 || CONFIG_CPU == DM320
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__TIMER_UNREGISTER();
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#endif
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pfn_timer = NULL;
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pfn_unregister = NULL;
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timer_prio = -1;
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}
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