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Rename CPU/COP_INT_CLR to CPU/COP_INT_DIS since it's really a 'write one to disable' register and hasn't anything to do with acknowledging interrupts-- that's handled at the module level.

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17683 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Michael Sevakis 2008-06-03 05:08:24 +00:00
parent 606d9d0c83
commit 191320cd0f
11 changed files with 23 additions and 23 deletions
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4
firmware/export/pp5002.h
View file

@ -105,12 +105,12 @@
#define CPU_INT_EN_STAT (*(volatile unsigned long *)(0xcf001020))
#define CPU_INT_EN (*(volatile unsigned long *)(0xcf001024))
#define CPU_INT_CLR (*(volatile unsigned long *)(0xcf001028))
#define CPU_INT_DIS (*(volatile unsigned long *)(0xcf001028))
#define CPU_INT_PRIORITY (*(volatile unsigned long *)(0xcf00102c))
#define COP_INT_EN_STAT (*(volatile unsigned long *)(0xcf001030))
#define COP_INT_EN (*(volatile unsigned long *)(0xcf001034))
#define COP_INT_CLR (*(volatile unsigned long *)(0xcf001038))
#define COP_INT_DIS (*(volatile unsigned long *)(0xcf001038))
#define COP_INT_PRIORITY (*(volatile unsigned long *)(0xcf00103c))
#define IDE_IRQ 1

4
firmware/export/pp5020.h
View file

@ -62,12 +62,12 @@
#define CPU_INT_EN_STAT (*(volatile unsigned long*)(0x60004020))
#define CPU_INT_EN (*(volatile unsigned long*)(0x60004024))
#define CPU_INT_CLR (*(volatile unsigned long*)(0x60004028))
#define CPU_INT_DIS (*(volatile unsigned long*)(0x60004028))
#define CPU_INT_PRIORITY (*(volatile unsigned long*)(0x6000402c))
#define COP_INT_EN_STAT (*(volatile unsigned long*)(0x60004030))
#define COP_INT_EN (*(volatile unsigned long*)(0x60004034))
#define COP_INT_CLR (*(volatile unsigned long*)(0x60004038))
#define COP_INT_DIS (*(volatile unsigned long*)(0x60004038))
#define COP_INT_PRIORITY (*(volatile unsigned long*)(0x6000403c))
#define CPU_HI_INT_STAT (*(volatile unsigned long*)(0x60004100))

2
firmware/rolo.c
View file

@ -142,7 +142,7 @@ void rolo_restart(const unsigned char* source, unsigned char* dest,
: : "a"(dest)
);
#elif defined(CPU_PP502x)
CPU_INT_CLR = -1;
CPU_INT_DIS = -1;
/* Flush cache */
flush_icache();

2
firmware/target/arm/ipod/button-1g-3g.c
View file

@ -167,7 +167,7 @@ static int ipod_3g_button_read(void)
void ipod_3g_button_int(void)
{
CPU_INT_CLR = GPIO_MASK;
CPU_INT_DIS = GPIO_MASK;
int_btn = ipod_3g_button_read();
CPU_INT_EN = GPIO_MASK;
}

4
firmware/target/arm/olympus/mrobe-100/power-mr100.c
View file

@ -63,8 +63,8 @@ void power_off(void)
disable_interrupt(IRQ_FIQ_STATUS);
/* Mask them on both cores */
CPU_INT_CLR = -1;
COP_INT_CLR = -1;
CPU_INT_DIS = -1;
COP_INT_DIS = -1;
while (1)
GPIOB_OUTPUT_VAL |= 0x80;

4
firmware/target/arm/philips/sa9200/power-sa9200.c
View file

@ -40,8 +40,8 @@ void power_off(void)
/* Stop interrupts on both cores */
disable_interrupt(IRQ_FIQ_STATUS);
COP_INT_CLR = -1;
CPU_INT_CLR = -1;
COP_INT_DIS = -1;
CPU_INT_DIS = -1;
/* Halt everything and wait for device to power off */
while (1)

4
firmware/target/arm/sandisk/power-c200_e200.c
View file

@ -40,8 +40,8 @@ void power_off(void)
/* Stop interrupts on both cores */
disable_interrupt(IRQ_FIQ_STATUS);
COP_INT_CLR = -1;
CPU_INT_CLR = -1;
COP_INT_DIS = -1;
CPU_INT_DIS = -1;
/* Halt everything and wait for device to power off */
while (1)

4
firmware/target/arm/system-pp5002.c
View file

@ -177,8 +177,8 @@ void system_init(void)
#endif
INT_FORCED_CLR = -1;
CPU_INT_CLR = -1;
COP_INT_CLR = -1;
CPU_INT_DIS = -1;
COP_INT_DIS = -1;
GPIOA_INT_EN = 0;
GPIOB_INT_EN = 0;

8
firmware/target/arm/system-pp502x.c
View file

@ -384,12 +384,12 @@ void system_init(void)
#endif
/* disable all irqs */
COP_HI_INT_CLR = -1;
CPU_HI_INT_CLR = -1;
COP_HI_INT_DIS = -1;
CPU_HI_INT_DIS = -1;
HI_INT_FORCED_CLR = -1;
COP_INT_CLR = -1;
CPU_INT_CLR = -1;
COP_INT_DIS = -1;
CPU_INT_DIS = -1;
INT_FORCED_CLR = -1;
GPIOA_INT_EN = 0;

2
firmware/target/arm/usb-drv-arc.c
View file

@ -475,7 +475,7 @@ void usb_drv_exit(void)
#if CONFIG_CPU == IMX31L
avic_disable_int(USB_OTG);
#else
CPU_INT_CLR = USB_MASK;
CPU_INT_DIS = USB_MASK;
#endif
cancel_cpu_boost();

8
firmware/timer.c
View file

@ -201,8 +201,8 @@ static bool timer_set(long cycles, bool start)
pfn_unregister();
pfn_unregister = NULL;
}
CPU_INT_CLR = TIMER2_MASK;
COP_INT_CLR = TIMER2_MASK;
CPU_INT_DIS = TIMER2_MASK;
COP_INT_DIS = TIMER2_MASK;
}
if (start || (cycles_new == -1)) /* within isr, cycles_new is "locked" */
TIMER2_CFG = 0xc0000000 | (cycles - 1); /* enable timer */
@ -311,8 +311,8 @@ void timer_unregister(void)
or_l((1<<10), &IMR); /* disable interrupt */
#elif defined(CPU_PP)
TIMER2_CFG = 0; /* stop timer 2 */
CPU_INT_CLR = TIMER2_MASK;
COP_INT_CLR = TIMER2_MASK;
CPU_INT_DIS = TIMER2_MASK;
COP_INT_DIS = TIMER2_MASK;
#elif CONFIG_CPU == PNX0101
TIMER1.ctrl &= ~0x80; /* disable timer 1 */
irq_disable_int(IRQ_TIMER1);