eac1ca22bd
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
405 lines
22 KiB
C
405 lines
22 KiB
C
/***************************************************************************
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* __________ __ ___.
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* Open \______ \ ____ ____ | | _\_ |__ _______ ___
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* Source | _// _ \_/ ___\| |/ /| __ \ / _ \ \/ /
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* Jukebox | | ( <_> ) \___| < | \_\ ( <_> > < <
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* Firmware |____|_ /\____/ \___ >__|_ \|___ /\____/__/\_ \
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* \/ \/ \/ \/ \/
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* This file was automatically generated by headergen, DO NOT EDIT it.
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* headergen version: 3.0.0
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* stmp3600 version: 2.4.0
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* stmp3600 authors: Amaury Pouly
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*
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* Copyright (C) 2015 by the authors
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This software is distributed on an "AS IS" basis, WITHOUT WARRANTY OF ANY
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* KIND, either express or implied.
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*
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****************************************************************************/
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#ifndef __HEADERGEN_STMP3600_PINCTRL_H__
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#define __HEADERGEN_STMP3600_PINCTRL_H__
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#define HW_PINCTRL_CTRL HW(PINCTRL_CTRL)
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#define HWA_PINCTRL_CTRL (0x80018000 + 0x0)
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#define HWT_PINCTRL_CTRL HWIO_32_RW
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#define HWN_PINCTRL_CTRL PINCTRL_CTRL
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#define HWI_PINCTRL_CTRL
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#define HW_PINCTRL_CTRL_SET HW(PINCTRL_CTRL_SET)
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#define HWA_PINCTRL_CTRL_SET (HWA_PINCTRL_CTRL + 0x4)
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#define HWT_PINCTRL_CTRL_SET HWIO_32_WO
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#define HWN_PINCTRL_CTRL_SET PINCTRL_CTRL
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#define HWI_PINCTRL_CTRL_SET
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#define HW_PINCTRL_CTRL_CLR HW(PINCTRL_CTRL_CLR)
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#define HWA_PINCTRL_CTRL_CLR (HWA_PINCTRL_CTRL + 0x8)
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#define HWT_PINCTRL_CTRL_CLR HWIO_32_WO
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#define HWN_PINCTRL_CTRL_CLR PINCTRL_CTRL
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#define HWI_PINCTRL_CTRL_CLR
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#define HW_PINCTRL_CTRL_TOG HW(PINCTRL_CTRL_TOG)
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#define HWA_PINCTRL_CTRL_TOG (HWA_PINCTRL_CTRL + 0xc)
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#define HWT_PINCTRL_CTRL_TOG HWIO_32_WO
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#define HWN_PINCTRL_CTRL_TOG PINCTRL_CTRL
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#define HWI_PINCTRL_CTRL_TOG
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#define BP_PINCTRL_CTRL_SFTRST 31
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#define BM_PINCTRL_CTRL_SFTRST 0x80000000
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#define BF_PINCTRL_CTRL_SFTRST(v) (((v) & 0x1) << 31)
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#define BFM_PINCTRL_CTRL_SFTRST(v) BM_PINCTRL_CTRL_SFTRST
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#define BF_PINCTRL_CTRL_SFTRST_V(e) BF_PINCTRL_CTRL_SFTRST(BV_PINCTRL_CTRL_SFTRST__##e)
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#define BFM_PINCTRL_CTRL_SFTRST_V(v) BM_PINCTRL_CTRL_SFTRST
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#define BP_PINCTRL_CTRL_CLKGATE 30
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#define BM_PINCTRL_CTRL_CLKGATE 0x40000000
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#define BF_PINCTRL_CTRL_CLKGATE(v) (((v) & 0x1) << 30)
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#define BFM_PINCTRL_CTRL_CLKGATE(v) BM_PINCTRL_CTRL_CLKGATE
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#define BF_PINCTRL_CTRL_CLKGATE_V(e) BF_PINCTRL_CTRL_CLKGATE(BV_PINCTRL_CTRL_CLKGATE__##e)
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#define BFM_PINCTRL_CTRL_CLKGATE_V(v) BM_PINCTRL_CTRL_CLKGATE
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#define BP_PINCTRL_CTRL_PRESENT3 29
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#define BM_PINCTRL_CTRL_PRESENT3 0x20000000
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#define BF_PINCTRL_CTRL_PRESENT3(v) (((v) & 0x1) << 29)
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#define BFM_PINCTRL_CTRL_PRESENT3(v) BM_PINCTRL_CTRL_PRESENT3
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#define BF_PINCTRL_CTRL_PRESENT3_V(e) BF_PINCTRL_CTRL_PRESENT3(BV_PINCTRL_CTRL_PRESENT3__##e)
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#define BFM_PINCTRL_CTRL_PRESENT3_V(v) BM_PINCTRL_CTRL_PRESENT3
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#define BP_PINCTRL_CTRL_PRESENT2 28
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#define BM_PINCTRL_CTRL_PRESENT2 0x10000000
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#define BF_PINCTRL_CTRL_PRESENT2(v) (((v) & 0x1) << 28)
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#define BFM_PINCTRL_CTRL_PRESENT2(v) BM_PINCTRL_CTRL_PRESENT2
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#define BF_PINCTRL_CTRL_PRESENT2_V(e) BF_PINCTRL_CTRL_PRESENT2(BV_PINCTRL_CTRL_PRESENT2__##e)
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#define BFM_PINCTRL_CTRL_PRESENT2_V(v) BM_PINCTRL_CTRL_PRESENT2
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#define BP_PINCTRL_CTRL_PRESENT1 27
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#define BM_PINCTRL_CTRL_PRESENT1 0x8000000
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#define BF_PINCTRL_CTRL_PRESENT1(v) (((v) & 0x1) << 27)
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#define BFM_PINCTRL_CTRL_PRESENT1(v) BM_PINCTRL_CTRL_PRESENT1
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#define BF_PINCTRL_CTRL_PRESENT1_V(e) BF_PINCTRL_CTRL_PRESENT1(BV_PINCTRL_CTRL_PRESENT1__##e)
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#define BFM_PINCTRL_CTRL_PRESENT1_V(v) BM_PINCTRL_CTRL_PRESENT1
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#define BP_PINCTRL_CTRL_PRESENT0 26
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#define BM_PINCTRL_CTRL_PRESENT0 0x4000000
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#define BF_PINCTRL_CTRL_PRESENT0(v) (((v) & 0x1) << 26)
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#define BFM_PINCTRL_CTRL_PRESENT0(v) BM_PINCTRL_CTRL_PRESENT0
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#define BF_PINCTRL_CTRL_PRESENT0_V(e) BF_PINCTRL_CTRL_PRESENT0(BV_PINCTRL_CTRL_PRESENT0__##e)
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#define BFM_PINCTRL_CTRL_PRESENT0_V(v) BM_PINCTRL_CTRL_PRESENT0
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#define BP_PINCTRL_CTRL_IRQOUT3 3
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#define BM_PINCTRL_CTRL_IRQOUT3 0x8
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#define BF_PINCTRL_CTRL_IRQOUT3(v) (((v) & 0x1) << 3)
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#define BFM_PINCTRL_CTRL_IRQOUT3(v) BM_PINCTRL_CTRL_IRQOUT3
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#define BF_PINCTRL_CTRL_IRQOUT3_V(e) BF_PINCTRL_CTRL_IRQOUT3(BV_PINCTRL_CTRL_IRQOUT3__##e)
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#define BFM_PINCTRL_CTRL_IRQOUT3_V(v) BM_PINCTRL_CTRL_IRQOUT3
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#define BP_PINCTRL_CTRL_IRQOUT2 2
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#define BM_PINCTRL_CTRL_IRQOUT2 0x4
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#define BF_PINCTRL_CTRL_IRQOUT2(v) (((v) & 0x1) << 2)
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#define BFM_PINCTRL_CTRL_IRQOUT2(v) BM_PINCTRL_CTRL_IRQOUT2
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#define BF_PINCTRL_CTRL_IRQOUT2_V(e) BF_PINCTRL_CTRL_IRQOUT2(BV_PINCTRL_CTRL_IRQOUT2__##e)
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#define BFM_PINCTRL_CTRL_IRQOUT2_V(v) BM_PINCTRL_CTRL_IRQOUT2
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#define BP_PINCTRL_CTRL_IRQOUT1 1
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#define BM_PINCTRL_CTRL_IRQOUT1 0x2
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#define BF_PINCTRL_CTRL_IRQOUT1(v) (((v) & 0x1) << 1)
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#define BFM_PINCTRL_CTRL_IRQOUT1(v) BM_PINCTRL_CTRL_IRQOUT1
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#define BF_PINCTRL_CTRL_IRQOUT1_V(e) BF_PINCTRL_CTRL_IRQOUT1(BV_PINCTRL_CTRL_IRQOUT1__##e)
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#define BFM_PINCTRL_CTRL_IRQOUT1_V(v) BM_PINCTRL_CTRL_IRQOUT1
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#define BP_PINCTRL_CTRL_IRQOUT0 0
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#define BM_PINCTRL_CTRL_IRQOUT0 0x1
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#define BF_PINCTRL_CTRL_IRQOUT0(v) (((v) & 0x1) << 0)
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#define BFM_PINCTRL_CTRL_IRQOUT0(v) BM_PINCTRL_CTRL_IRQOUT0
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#define BF_PINCTRL_CTRL_IRQOUT0_V(e) BF_PINCTRL_CTRL_IRQOUT0(BV_PINCTRL_CTRL_IRQOUT0__##e)
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#define BFM_PINCTRL_CTRL_IRQOUT0_V(v) BM_PINCTRL_CTRL_IRQOUT0
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#define HW_PINCTRL_MUXSELLn(_n1) HW(PINCTRL_MUXSELLn(_n1))
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#define HWA_PINCTRL_MUXSELLn(_n1) (0x80018000 + 0x10 + (_n1) * 0x100)
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#define HWT_PINCTRL_MUXSELLn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_MUXSELLn(_n1) PINCTRL_MUXSELLn
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#define HWI_PINCTRL_MUXSELLn(_n1) (_n1)
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#define HW_PINCTRL_MUXSELLn_SET(_n1) HW(PINCTRL_MUXSELLn_SET(_n1))
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#define HWA_PINCTRL_MUXSELLn_SET(_n1) (HWA_PINCTRL_MUXSELLn(_n1) + 0x4)
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#define HWT_PINCTRL_MUXSELLn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_MUXSELLn_SET(_n1) PINCTRL_MUXSELLn
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#define HWI_PINCTRL_MUXSELLn_SET(_n1) (_n1)
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#define HW_PINCTRL_MUXSELLn_CLR(_n1) HW(PINCTRL_MUXSELLn_CLR(_n1))
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#define HWA_PINCTRL_MUXSELLn_CLR(_n1) (HWA_PINCTRL_MUXSELLn(_n1) + 0x8)
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#define HWT_PINCTRL_MUXSELLn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_MUXSELLn_CLR(_n1) PINCTRL_MUXSELLn
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#define HWI_PINCTRL_MUXSELLn_CLR(_n1) (_n1)
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#define HW_PINCTRL_MUXSELLn_TOG(_n1) HW(PINCTRL_MUXSELLn_TOG(_n1))
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#define HWA_PINCTRL_MUXSELLn_TOG(_n1) (HWA_PINCTRL_MUXSELLn(_n1) + 0xc)
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#define HWT_PINCTRL_MUXSELLn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_MUXSELLn_TOG(_n1) PINCTRL_MUXSELLn
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#define HWI_PINCTRL_MUXSELLn_TOG(_n1) (_n1)
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#define BP_PINCTRL_MUXSELLn_BITS 0
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#define BM_PINCTRL_MUXSELLn_BITS 0xffffffff
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#define BF_PINCTRL_MUXSELLn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_MUXSELLn_BITS(v) BM_PINCTRL_MUXSELLn_BITS
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#define BF_PINCTRL_MUXSELLn_BITS_V(e) BF_PINCTRL_MUXSELLn_BITS(BV_PINCTRL_MUXSELLn_BITS__##e)
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#define BFM_PINCTRL_MUXSELLn_BITS_V(v) BM_PINCTRL_MUXSELLn_BITS
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#define HW_PINCTRL_MUXSELHn(_n1) HW(PINCTRL_MUXSELHn(_n1))
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#define HWA_PINCTRL_MUXSELHn(_n1) (0x80018000 + 0x20 + (_n1) * 0x100)
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#define HWT_PINCTRL_MUXSELHn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_MUXSELHn(_n1) PINCTRL_MUXSELHn
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#define HWI_PINCTRL_MUXSELHn(_n1) (_n1)
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#define HW_PINCTRL_MUXSELHn_SET(_n1) HW(PINCTRL_MUXSELHn_SET(_n1))
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#define HWA_PINCTRL_MUXSELHn_SET(_n1) (HWA_PINCTRL_MUXSELHn(_n1) + 0x4)
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#define HWT_PINCTRL_MUXSELHn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_MUXSELHn_SET(_n1) PINCTRL_MUXSELHn
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#define HWI_PINCTRL_MUXSELHn_SET(_n1) (_n1)
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#define HW_PINCTRL_MUXSELHn_CLR(_n1) HW(PINCTRL_MUXSELHn_CLR(_n1))
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#define HWA_PINCTRL_MUXSELHn_CLR(_n1) (HWA_PINCTRL_MUXSELHn(_n1) + 0x8)
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#define HWT_PINCTRL_MUXSELHn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_MUXSELHn_CLR(_n1) PINCTRL_MUXSELHn
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#define HWI_PINCTRL_MUXSELHn_CLR(_n1) (_n1)
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#define HW_PINCTRL_MUXSELHn_TOG(_n1) HW(PINCTRL_MUXSELHn_TOG(_n1))
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#define HWA_PINCTRL_MUXSELHn_TOG(_n1) (HWA_PINCTRL_MUXSELHn(_n1) + 0xc)
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#define HWT_PINCTRL_MUXSELHn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_MUXSELHn_TOG(_n1) PINCTRL_MUXSELHn
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#define HWI_PINCTRL_MUXSELHn_TOG(_n1) (_n1)
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#define BP_PINCTRL_MUXSELHn_BITS 0
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#define BM_PINCTRL_MUXSELHn_BITS 0xffffffff
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#define BF_PINCTRL_MUXSELHn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_MUXSELHn_BITS(v) BM_PINCTRL_MUXSELHn_BITS
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#define BF_PINCTRL_MUXSELHn_BITS_V(e) BF_PINCTRL_MUXSELHn_BITS(BV_PINCTRL_MUXSELHn_BITS__##e)
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#define BFM_PINCTRL_MUXSELHn_BITS_V(v) BM_PINCTRL_MUXSELHn_BITS
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#define HW_PINCTRL_DRIVEn(_n1) HW(PINCTRL_DRIVEn(_n1))
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#define HWA_PINCTRL_DRIVEn(_n1) (0x80018000 + 0x30 + (_n1) * 0x100)
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#define HWT_PINCTRL_DRIVEn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_DRIVEn(_n1) PINCTRL_DRIVEn
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#define HWI_PINCTRL_DRIVEn(_n1) (_n1)
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#define HW_PINCTRL_DRIVEn_SET(_n1) HW(PINCTRL_DRIVEn_SET(_n1))
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#define HWA_PINCTRL_DRIVEn_SET(_n1) (HWA_PINCTRL_DRIVEn(_n1) + 0x4)
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#define HWT_PINCTRL_DRIVEn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DRIVEn_SET(_n1) PINCTRL_DRIVEn
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#define HWI_PINCTRL_DRIVEn_SET(_n1) (_n1)
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#define HW_PINCTRL_DRIVEn_CLR(_n1) HW(PINCTRL_DRIVEn_CLR(_n1))
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#define HWA_PINCTRL_DRIVEn_CLR(_n1) (HWA_PINCTRL_DRIVEn(_n1) + 0x8)
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#define HWT_PINCTRL_DRIVEn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DRIVEn_CLR(_n1) PINCTRL_DRIVEn
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#define HWI_PINCTRL_DRIVEn_CLR(_n1) (_n1)
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#define HW_PINCTRL_DRIVEn_TOG(_n1) HW(PINCTRL_DRIVEn_TOG(_n1))
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#define HWA_PINCTRL_DRIVEn_TOG(_n1) (HWA_PINCTRL_DRIVEn(_n1) + 0xc)
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#define HWT_PINCTRL_DRIVEn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DRIVEn_TOG(_n1) PINCTRL_DRIVEn
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#define HWI_PINCTRL_DRIVEn_TOG(_n1) (_n1)
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#define BP_PINCTRL_DRIVEn_BITS 0
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#define BM_PINCTRL_DRIVEn_BITS 0xffffffff
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#define BF_PINCTRL_DRIVEn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_DRIVEn_BITS(v) BM_PINCTRL_DRIVEn_BITS
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#define BF_PINCTRL_DRIVEn_BITS_V(e) BF_PINCTRL_DRIVEn_BITS(BV_PINCTRL_DRIVEn_BITS__##e)
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#define BFM_PINCTRL_DRIVEn_BITS_V(v) BM_PINCTRL_DRIVEn_BITS
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#define HW_PINCTRL_DOUTn(_n1) HW(PINCTRL_DOUTn(_n1))
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#define HWA_PINCTRL_DOUTn(_n1) (0x80018000 + 0x50 + (_n1) * 0x100)
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#define HWT_PINCTRL_DOUTn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_DOUTn(_n1) PINCTRL_DOUTn
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#define HWI_PINCTRL_DOUTn(_n1) (_n1)
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#define HW_PINCTRL_DOUTn_SET(_n1) HW(PINCTRL_DOUTn_SET(_n1))
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#define HWA_PINCTRL_DOUTn_SET(_n1) (HWA_PINCTRL_DOUTn(_n1) + 0x4)
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#define HWT_PINCTRL_DOUTn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DOUTn_SET(_n1) PINCTRL_DOUTn
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#define HWI_PINCTRL_DOUTn_SET(_n1) (_n1)
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#define HW_PINCTRL_DOUTn_CLR(_n1) HW(PINCTRL_DOUTn_CLR(_n1))
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#define HWA_PINCTRL_DOUTn_CLR(_n1) (HWA_PINCTRL_DOUTn(_n1) + 0x8)
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#define HWT_PINCTRL_DOUTn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DOUTn_CLR(_n1) PINCTRL_DOUTn
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#define HWI_PINCTRL_DOUTn_CLR(_n1) (_n1)
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#define HW_PINCTRL_DOUTn_TOG(_n1) HW(PINCTRL_DOUTn_TOG(_n1))
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#define HWA_PINCTRL_DOUTn_TOG(_n1) (HWA_PINCTRL_DOUTn(_n1) + 0xc)
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#define HWT_PINCTRL_DOUTn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DOUTn_TOG(_n1) PINCTRL_DOUTn
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#define HWI_PINCTRL_DOUTn_TOG(_n1) (_n1)
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#define BP_PINCTRL_DOUTn_BITS 0
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#define BM_PINCTRL_DOUTn_BITS 0xffffffff
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#define BF_PINCTRL_DOUTn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_DOUTn_BITS(v) BM_PINCTRL_DOUTn_BITS
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#define BF_PINCTRL_DOUTn_BITS_V(e) BF_PINCTRL_DOUTn_BITS(BV_PINCTRL_DOUTn_BITS__##e)
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#define BFM_PINCTRL_DOUTn_BITS_V(v) BM_PINCTRL_DOUTn_BITS
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#define HW_PINCTRL_DINn(_n1) HW(PINCTRL_DINn(_n1))
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#define HWA_PINCTRL_DINn(_n1) (0x80018000 + 0x60 + (_n1) * 0x100)
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#define HWT_PINCTRL_DINn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_DINn(_n1) PINCTRL_DINn
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#define HWI_PINCTRL_DINn(_n1) (_n1)
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#define HW_PINCTRL_DINn_SET(_n1) HW(PINCTRL_DINn_SET(_n1))
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#define HWA_PINCTRL_DINn_SET(_n1) (HWA_PINCTRL_DINn(_n1) + 0x4)
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#define HWT_PINCTRL_DINn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DINn_SET(_n1) PINCTRL_DINn
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#define HWI_PINCTRL_DINn_SET(_n1) (_n1)
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#define HW_PINCTRL_DINn_CLR(_n1) HW(PINCTRL_DINn_CLR(_n1))
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#define HWA_PINCTRL_DINn_CLR(_n1) (HWA_PINCTRL_DINn(_n1) + 0x8)
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#define HWT_PINCTRL_DINn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DINn_CLR(_n1) PINCTRL_DINn
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#define HWI_PINCTRL_DINn_CLR(_n1) (_n1)
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#define HW_PINCTRL_DINn_TOG(_n1) HW(PINCTRL_DINn_TOG(_n1))
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#define HWA_PINCTRL_DINn_TOG(_n1) (HWA_PINCTRL_DINn(_n1) + 0xc)
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#define HWT_PINCTRL_DINn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DINn_TOG(_n1) PINCTRL_DINn
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#define HWI_PINCTRL_DINn_TOG(_n1) (_n1)
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#define BP_PINCTRL_DINn_BITS 0
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#define BM_PINCTRL_DINn_BITS 0xffffffff
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#define BF_PINCTRL_DINn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_DINn_BITS(v) BM_PINCTRL_DINn_BITS
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#define BF_PINCTRL_DINn_BITS_V(e) BF_PINCTRL_DINn_BITS(BV_PINCTRL_DINn_BITS__##e)
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#define BFM_PINCTRL_DINn_BITS_V(v) BM_PINCTRL_DINn_BITS
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#define HW_PINCTRL_DOEn(_n1) HW(PINCTRL_DOEn(_n1))
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#define HWA_PINCTRL_DOEn(_n1) (0x80018000 + 0x70 + (_n1) * 0x100)
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#define HWT_PINCTRL_DOEn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_DOEn(_n1) PINCTRL_DOEn
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#define HWI_PINCTRL_DOEn(_n1) (_n1)
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#define HW_PINCTRL_DOEn_SET(_n1) HW(PINCTRL_DOEn_SET(_n1))
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#define HWA_PINCTRL_DOEn_SET(_n1) (HWA_PINCTRL_DOEn(_n1) + 0x4)
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#define HWT_PINCTRL_DOEn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DOEn_SET(_n1) PINCTRL_DOEn
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#define HWI_PINCTRL_DOEn_SET(_n1) (_n1)
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#define HW_PINCTRL_DOEn_CLR(_n1) HW(PINCTRL_DOEn_CLR(_n1))
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#define HWA_PINCTRL_DOEn_CLR(_n1) (HWA_PINCTRL_DOEn(_n1) + 0x8)
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#define HWT_PINCTRL_DOEn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DOEn_CLR(_n1) PINCTRL_DOEn
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#define HWI_PINCTRL_DOEn_CLR(_n1) (_n1)
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#define HW_PINCTRL_DOEn_TOG(_n1) HW(PINCTRL_DOEn_TOG(_n1))
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#define HWA_PINCTRL_DOEn_TOG(_n1) (HWA_PINCTRL_DOEn(_n1) + 0xc)
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#define HWT_PINCTRL_DOEn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_DOEn_TOG(_n1) PINCTRL_DOEn
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#define HWI_PINCTRL_DOEn_TOG(_n1) (_n1)
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#define BP_PINCTRL_DOEn_BITS 0
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#define BM_PINCTRL_DOEn_BITS 0xffffffff
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#define BF_PINCTRL_DOEn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_DOEn_BITS(v) BM_PINCTRL_DOEn_BITS
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#define BF_PINCTRL_DOEn_BITS_V(e) BF_PINCTRL_DOEn_BITS(BV_PINCTRL_DOEn_BITS__##e)
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#define BFM_PINCTRL_DOEn_BITS_V(v) BM_PINCTRL_DOEn_BITS
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#define HW_PINCTRL_PIN2IRQn(_n1) HW(PINCTRL_PIN2IRQn(_n1))
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#define HWA_PINCTRL_PIN2IRQn(_n1) (0x80018000 + 0x80 + (_n1) * 0x100)
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#define HWT_PINCTRL_PIN2IRQn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_PIN2IRQn(_n1) PINCTRL_PIN2IRQn
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#define HWI_PINCTRL_PIN2IRQn(_n1) (_n1)
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#define HW_PINCTRL_PIN2IRQn_SET(_n1) HW(PINCTRL_PIN2IRQn_SET(_n1))
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#define HWA_PINCTRL_PIN2IRQn_SET(_n1) (HWA_PINCTRL_PIN2IRQn(_n1) + 0x4)
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#define HWT_PINCTRL_PIN2IRQn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_PIN2IRQn_SET(_n1) PINCTRL_PIN2IRQn
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#define HWI_PINCTRL_PIN2IRQn_SET(_n1) (_n1)
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#define HW_PINCTRL_PIN2IRQn_CLR(_n1) HW(PINCTRL_PIN2IRQn_CLR(_n1))
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#define HWA_PINCTRL_PIN2IRQn_CLR(_n1) (HWA_PINCTRL_PIN2IRQn(_n1) + 0x8)
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#define HWT_PINCTRL_PIN2IRQn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_PIN2IRQn_CLR(_n1) PINCTRL_PIN2IRQn
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#define HWI_PINCTRL_PIN2IRQn_CLR(_n1) (_n1)
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#define HW_PINCTRL_PIN2IRQn_TOG(_n1) HW(PINCTRL_PIN2IRQn_TOG(_n1))
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#define HWA_PINCTRL_PIN2IRQn_TOG(_n1) (HWA_PINCTRL_PIN2IRQn(_n1) + 0xc)
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#define HWT_PINCTRL_PIN2IRQn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_PIN2IRQn_TOG(_n1) PINCTRL_PIN2IRQn
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#define HWI_PINCTRL_PIN2IRQn_TOG(_n1) (_n1)
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#define BP_PINCTRL_PIN2IRQn_BITS 0
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#define BM_PINCTRL_PIN2IRQn_BITS 0xffffffff
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#define BF_PINCTRL_PIN2IRQn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_PIN2IRQn_BITS(v) BM_PINCTRL_PIN2IRQn_BITS
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#define BF_PINCTRL_PIN2IRQn_BITS_V(e) BF_PINCTRL_PIN2IRQn_BITS(BV_PINCTRL_PIN2IRQn_BITS__##e)
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#define BFM_PINCTRL_PIN2IRQn_BITS_V(v) BM_PINCTRL_PIN2IRQn_BITS
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#define HW_PINCTRL_IRQENn(_n1) HW(PINCTRL_IRQENn(_n1))
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#define HWA_PINCTRL_IRQENn(_n1) (0x80018000 + 0x90 + (_n1) * 0x100)
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#define HWT_PINCTRL_IRQENn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_IRQENn(_n1) PINCTRL_IRQENn
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#define HWI_PINCTRL_IRQENn(_n1) (_n1)
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#define HW_PINCTRL_IRQENn_SET(_n1) HW(PINCTRL_IRQENn_SET(_n1))
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#define HWA_PINCTRL_IRQENn_SET(_n1) (HWA_PINCTRL_IRQENn(_n1) + 0x4)
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#define HWT_PINCTRL_IRQENn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQENn_SET(_n1) PINCTRL_IRQENn
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#define HWI_PINCTRL_IRQENn_SET(_n1) (_n1)
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#define HW_PINCTRL_IRQENn_CLR(_n1) HW(PINCTRL_IRQENn_CLR(_n1))
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#define HWA_PINCTRL_IRQENn_CLR(_n1) (HWA_PINCTRL_IRQENn(_n1) + 0x8)
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#define HWT_PINCTRL_IRQENn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQENn_CLR(_n1) PINCTRL_IRQENn
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#define HWI_PINCTRL_IRQENn_CLR(_n1) (_n1)
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#define HW_PINCTRL_IRQENn_TOG(_n1) HW(PINCTRL_IRQENn_TOG(_n1))
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#define HWA_PINCTRL_IRQENn_TOG(_n1) (HWA_PINCTRL_IRQENn(_n1) + 0xc)
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#define HWT_PINCTRL_IRQENn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQENn_TOG(_n1) PINCTRL_IRQENn
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#define HWI_PINCTRL_IRQENn_TOG(_n1) (_n1)
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#define BP_PINCTRL_IRQENn_BITS 0
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#define BM_PINCTRL_IRQENn_BITS 0xffffffff
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#define BF_PINCTRL_IRQENn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_IRQENn_BITS(v) BM_PINCTRL_IRQENn_BITS
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#define BF_PINCTRL_IRQENn_BITS_V(e) BF_PINCTRL_IRQENn_BITS(BV_PINCTRL_IRQENn_BITS__##e)
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#define BFM_PINCTRL_IRQENn_BITS_V(v) BM_PINCTRL_IRQENn_BITS
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#define HW_PINCTRL_IRQLEVELn(_n1) HW(PINCTRL_IRQLEVELn(_n1))
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#define HWA_PINCTRL_IRQLEVELn(_n1) (0x80018000 + 0xa0 + (_n1) * 0x100)
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#define HWT_PINCTRL_IRQLEVELn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_IRQLEVELn(_n1) PINCTRL_IRQLEVELn
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#define HWI_PINCTRL_IRQLEVELn(_n1) (_n1)
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#define HW_PINCTRL_IRQLEVELn_SET(_n1) HW(PINCTRL_IRQLEVELn_SET(_n1))
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#define HWA_PINCTRL_IRQLEVELn_SET(_n1) (HWA_PINCTRL_IRQLEVELn(_n1) + 0x4)
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#define HWT_PINCTRL_IRQLEVELn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQLEVELn_SET(_n1) PINCTRL_IRQLEVELn
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#define HWI_PINCTRL_IRQLEVELn_SET(_n1) (_n1)
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#define HW_PINCTRL_IRQLEVELn_CLR(_n1) HW(PINCTRL_IRQLEVELn_CLR(_n1))
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#define HWA_PINCTRL_IRQLEVELn_CLR(_n1) (HWA_PINCTRL_IRQLEVELn(_n1) + 0x8)
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#define HWT_PINCTRL_IRQLEVELn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQLEVELn_CLR(_n1) PINCTRL_IRQLEVELn
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#define HWI_PINCTRL_IRQLEVELn_CLR(_n1) (_n1)
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#define HW_PINCTRL_IRQLEVELn_TOG(_n1) HW(PINCTRL_IRQLEVELn_TOG(_n1))
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#define HWA_PINCTRL_IRQLEVELn_TOG(_n1) (HWA_PINCTRL_IRQLEVELn(_n1) + 0xc)
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#define HWT_PINCTRL_IRQLEVELn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQLEVELn_TOG(_n1) PINCTRL_IRQLEVELn
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#define HWI_PINCTRL_IRQLEVELn_TOG(_n1) (_n1)
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#define BP_PINCTRL_IRQLEVELn_BITS 0
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#define BM_PINCTRL_IRQLEVELn_BITS 0xffffffff
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#define BF_PINCTRL_IRQLEVELn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_IRQLEVELn_BITS(v) BM_PINCTRL_IRQLEVELn_BITS
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#define BF_PINCTRL_IRQLEVELn_BITS_V(e) BF_PINCTRL_IRQLEVELn_BITS(BV_PINCTRL_IRQLEVELn_BITS__##e)
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#define BFM_PINCTRL_IRQLEVELn_BITS_V(v) BM_PINCTRL_IRQLEVELn_BITS
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#define HW_PINCTRL_IRQPOLn(_n1) HW(PINCTRL_IRQPOLn(_n1))
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#define HWA_PINCTRL_IRQPOLn(_n1) (0x80018000 + 0xb0 + (_n1) * 0x100)
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#define HWT_PINCTRL_IRQPOLn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_IRQPOLn(_n1) PINCTRL_IRQPOLn
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#define HWI_PINCTRL_IRQPOLn(_n1) (_n1)
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#define HW_PINCTRL_IRQPOLn_SET(_n1) HW(PINCTRL_IRQPOLn_SET(_n1))
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#define HWA_PINCTRL_IRQPOLn_SET(_n1) (HWA_PINCTRL_IRQPOLn(_n1) + 0x4)
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#define HWT_PINCTRL_IRQPOLn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQPOLn_SET(_n1) PINCTRL_IRQPOLn
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#define HWI_PINCTRL_IRQPOLn_SET(_n1) (_n1)
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#define HW_PINCTRL_IRQPOLn_CLR(_n1) HW(PINCTRL_IRQPOLn_CLR(_n1))
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#define HWA_PINCTRL_IRQPOLn_CLR(_n1) (HWA_PINCTRL_IRQPOLn(_n1) + 0x8)
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#define HWT_PINCTRL_IRQPOLn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQPOLn_CLR(_n1) PINCTRL_IRQPOLn
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#define HWI_PINCTRL_IRQPOLn_CLR(_n1) (_n1)
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#define HW_PINCTRL_IRQPOLn_TOG(_n1) HW(PINCTRL_IRQPOLn_TOG(_n1))
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#define HWA_PINCTRL_IRQPOLn_TOG(_n1) (HWA_PINCTRL_IRQPOLn(_n1) + 0xc)
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#define HWT_PINCTRL_IRQPOLn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQPOLn_TOG(_n1) PINCTRL_IRQPOLn
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#define HWI_PINCTRL_IRQPOLn_TOG(_n1) (_n1)
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#define BP_PINCTRL_IRQPOLn_BITS 0
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#define BM_PINCTRL_IRQPOLn_BITS 0xffffffff
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#define BF_PINCTRL_IRQPOLn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_IRQPOLn_BITS(v) BM_PINCTRL_IRQPOLn_BITS
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#define BF_PINCTRL_IRQPOLn_BITS_V(e) BF_PINCTRL_IRQPOLn_BITS(BV_PINCTRL_IRQPOLn_BITS__##e)
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#define BFM_PINCTRL_IRQPOLn_BITS_V(v) BM_PINCTRL_IRQPOLn_BITS
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#define HW_PINCTRL_IRQSTATn(_n1) HW(PINCTRL_IRQSTATn(_n1))
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#define HWA_PINCTRL_IRQSTATn(_n1) (0x80018000 + 0xc0 + (_n1) * 0x100)
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#define HWT_PINCTRL_IRQSTATn(_n1) HWIO_32_RW
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#define HWN_PINCTRL_IRQSTATn(_n1) PINCTRL_IRQSTATn
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#define HWI_PINCTRL_IRQSTATn(_n1) (_n1)
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#define HW_PINCTRL_IRQSTATn_SET(_n1) HW(PINCTRL_IRQSTATn_SET(_n1))
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#define HWA_PINCTRL_IRQSTATn_SET(_n1) (HWA_PINCTRL_IRQSTATn(_n1) + 0x4)
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#define HWT_PINCTRL_IRQSTATn_SET(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQSTATn_SET(_n1) PINCTRL_IRQSTATn
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#define HWI_PINCTRL_IRQSTATn_SET(_n1) (_n1)
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#define HW_PINCTRL_IRQSTATn_CLR(_n1) HW(PINCTRL_IRQSTATn_CLR(_n1))
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#define HWA_PINCTRL_IRQSTATn_CLR(_n1) (HWA_PINCTRL_IRQSTATn(_n1) + 0x8)
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#define HWT_PINCTRL_IRQSTATn_CLR(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQSTATn_CLR(_n1) PINCTRL_IRQSTATn
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#define HWI_PINCTRL_IRQSTATn_CLR(_n1) (_n1)
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#define HW_PINCTRL_IRQSTATn_TOG(_n1) HW(PINCTRL_IRQSTATn_TOG(_n1))
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#define HWA_PINCTRL_IRQSTATn_TOG(_n1) (HWA_PINCTRL_IRQSTATn(_n1) + 0xc)
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#define HWT_PINCTRL_IRQSTATn_TOG(_n1) HWIO_32_WO
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#define HWN_PINCTRL_IRQSTATn_TOG(_n1) PINCTRL_IRQSTATn
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#define HWI_PINCTRL_IRQSTATn_TOG(_n1) (_n1)
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#define BP_PINCTRL_IRQSTATn_BITS 0
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#define BM_PINCTRL_IRQSTATn_BITS 0xffffffff
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#define BF_PINCTRL_IRQSTATn_BITS(v) (((v) & 0xffffffff) << 0)
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#define BFM_PINCTRL_IRQSTATn_BITS(v) BM_PINCTRL_IRQSTATn_BITS
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#define BF_PINCTRL_IRQSTATn_BITS_V(e) BF_PINCTRL_IRQSTATn_BITS(BV_PINCTRL_IRQSTATn_BITS__##e)
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#define BFM_PINCTRL_IRQSTATn_BITS_V(v) BM_PINCTRL_IRQSTATn_BITS
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#endif /* __HEADERGEN_STMP3600_PINCTRL_H__*/
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