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14 commits

Author SHA1 Message Date
Thomas Martitz
22a28f9caa Add missing kernel.h includes (hopefully all of them). 
Change-Id: I9c1825296a788587b8d494d8514b3314847b0ff0
 2014-01-05 20:32:09 +01:00
Andree Buschmann
e4a233ed9b Derive clock and timer defines from frequency of external source. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28791 a1c6a512-1295-4272-9138-f99709370657
 2010-12-11 09:39:33 +00:00
Andree Buschmann
e464656b88 Implement udelay() for S5L870x. Exchange sleep() with udelay() during CPU voltage scaling. Voltage scaling was measured stable with 50us delay, to have some headroom we use 100us. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28606 a1c6a512-1295-4272-9138-f99709370657
 2010-11-15 21:13:58 +00:00
Michael Sparmann
d41612ff03 Remove PROC_NEEDS_CACHEALIGN for Nano2G again, it's only needed for PP 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26996 a1c6a512-1295-4272-9138-f99709370657
 2010-06-20 17:35:02 +00:00
Michael Sparmann
27af11af5e Fix misspelled STORAGE_WANTS_ALIGN in s5l8700/system-target.h. Also add PROC_NEEDS_CACHEALIGN. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26985 a1c6a512-1295-4272-9138-f99709370657
 2010-06-20 12:35:29 +00:00
Rafaël Carré
f830fa79e5 s5l870x / ipod nano2g: include common mmu-arm.h 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25635 a1c6a512-1295-4272-9138-f99709370657
 2010-04-13 16:05:11 +00:00
Rafaël Carré
680fcd827d Move CACHEALIGN_BITS to cpu headers 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25633 a1c6a512-1295-4272-9138-f99709370657
 2010-04-13 15:50:08 +00:00
Rafaël Carré
b6065a8ceb Use STORAGE_WANTS_ALIGN to make clear it's not a strict necessity 
Define PROC_NEEDS_CACHEALIGN only for PP

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25339 a1c6a512-1295-4272-9138-f99709370657
 2010-03-26 00:11:50 +00:00
Rafaël Carré
a8d1690ffe Make storage alignement use cache alignement macros 
Introduce STORAGE_ALIGN_DOWN, STORAGE_PAD (using new CACHE_PAD) and
STORAGE_OVERLAP (using new CACHE_OVERLAP), make them useful only when
PROC_NEEDS_CACHEALIGN and STORAGE_NEEDS_ALIGN are defined

Modify PP and nano2g system-target.h accordingly

git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25336 a1c6a512-1295-4272-9138-f99709370657
 2010-03-25 23:01:56 +00:00
Michael Sparmann
c9dd93e286 Adjust the iPod Nano 2G CPU clock freq again, this time to an exact value. Also add hardware defines for the 9th DMA channel we discovered on the S5L8701, and fix the µsec timer (there were missing braces). 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23338 a1c6a512-1295-4272-9138-f99709370657
 2009-10-24 23:27:13 +00:00
Michael Sparmann
3ac50ca9ff Fix S5L870x cache coherency functions. They were split into a different file, as changes were needed all over the place. 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23239 a1c6a512-1295-4272-9138-f99709370657
 2009-10-17 23:06:45 +00:00
Michael Sparmann
a931acd3ab Added S5L870X cache coherency support 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@23058 a1c6a512-1295-4272-9138-f99709370657
 2009-10-09 21:41:57 +00:00
Daniel Stenberg
2acc0ac542 Updated our source code header to explicitly mention that we are GPL v2 or 
later. We still need to hunt down snippets used that are not. 1324 modified
files...
http://www.rockbox.org/mail/archive/rockbox-dev-archive-2008-06/0060.shtml


git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17847 a1c6a512-1295-4272-9138-f99709370657
 2008-06-28 18:10:04 +00:00
Marcoen Hirschberg
7b10ef9a7c initial Meizu M6SL port (take 2) 
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@17819 a1c6a512-1295-4272-9138-f99709370657
 2008-06-27 23:24:34 +00:00