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Move CACHEALIGN_BITS to cpu headers

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git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25633 a1c6a512-1295-4272-9138-f99709370657
This commit is contained in:
Rafaël Carré 2010-04-13 15:50:08 +00:00
parent d0af7f9601
commit 680fcd827d
5 changed files with 7 additions and 2 deletions
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3
firmware/export/pp5002.h
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@ -22,6 +22,9 @@
#define __PP5002_H__
/* Much info gleaned and/or copied from the iPodLinux project. */
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define DRAM_START 0x28000000
/* LCD bridge */

2
firmware/export/pp5020.h
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@ -23,6 +23,8 @@
/* All info gleaned and/or copied from the iPodLinux project. */
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
/* PCM addresses for obtaining buffers will be what DMA is using (physical) */
#define HAVE_PCM_DMA_ADDRESS

2
firmware/export/s5l8700.h
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@ -27,6 +27,8 @@
#define TIMER_FREQ 47923200L
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
/* 04. CALMADM2E */
/* Following registers are mapped on IO Area in data memory area of Calm. */

1
firmware/target/arm/s5l8700/system-target.h
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@ -29,7 +29,6 @@
#define CPUFREQ_NORMAL 47923200
#define CPUFREQ_MAX 191692800
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#define WANTS_STORAGE_ALIGN
#define inl(a) (*(volatile unsigned long *) (a))

1
firmware/target/arm/system-target.h
View file

@ -161,7 +161,6 @@ static inline void wake_core(int core)
/* Certain data needs to be out of the way of cache line interference
* such as data for COP use or for use with UNCACHED_ADDR */
#define PROC_NEEDS_CACHEALIGN
#define CACHEALIGN_BITS (4) /* 2^4 = 16 bytes */
#if defined(CPU_PP502x) && defined(HAVE_ATA_DMA)
#define STORAGE_WANTS_ALIGN