Michael Sevakis
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480c663e5b
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i.MX31: Now that it matters because there's a debug screeen that allows changing things while running, some DVFS/DPTC stuff has to be done more carefully. Trim out some stuff and group functions better as well.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29122 a1c6a512-1295-4272-9138-f99709370657
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2011-01-23 20:21:35 +00:00 |
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Michael Sevakis
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98246b82b9
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i.MX31: Add a debug menu to play around with DVFS/DPTC settings for fun, testing or benchmarking purposes. Can set the CPU frequency working point, whether DPTC voltage scaling is enabled and change the software-programmable load tracking weights.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@29113 a1c6a512-1295-4272-9138-f99709370657
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2011-01-22 16:58:17 +00:00 |
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Michael Sevakis
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9d97ee1b54
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Gigabeat S/i.MX31: Take care of an interrupt priority inversion that can happen during PCM callback lockout when DVFS switches frequecies during the lockout, preventing a thread from unlocking the callback until DVFS finishes, causing an SSI FIFO underrun. Hadn't thought of an acceptable way to deal with it before.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@28996 a1c6a512-1295-4272-9138-f99709370657
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2011-01-07 20:40:36 +00:00 |
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Michael Sevakis
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a36a498c57
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i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657
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2010-05-06 03:23:51 +00:00 |
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Michael Sevakis
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11cca264ff
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i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
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2010-04-23 15:32:50 +00:00 |
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Michael Sevakis
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87eea33def
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Gigabeat S (imx31): Begin voltage and frequency scaling code. For now, to avoid overdrive voltage, just lower core voltage to 1.35V since voltage scaling shouldn't be required for frequencies lower than 399 MHz (according to Freescale BSP, which set all working points to 1.35V for those frequencies). Perhaps battery life will improve as well (cross fingers :).
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25506 a1c6a512-1295-4272-9138-f99709370657
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2010-04-07 03:43:48 +00:00 |
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