This screen allows to put the device in a special mode where:
- charging is disabled
- device only draws power from 5V (thus battery is untouched)
This is useful to measure the device consumption by measuring directly
the usb power consumption.
Change-Id: I2716ced0a5bb33c3c9a2607f2d17a0ce02f5689c
Per Freescale recommandation, we need to ramp up the 4.2V rail before enabling
charging. Ramping should be done at 1 step/10ms, but the old code did 1 step/1s
because the powermgmt_step() function is called once every second. Use a tick
task to ramp up much faster.
Change-Id: I9a52bdd0c2ba5426d83ed42db8db7ecce2fea1f7
The old code used button_get() to read the button status and wait for a
key to leave the panic screen. This is broken since when IRQ are disable,
the button mask is not updated anymore for touchpad and adc buttons. For
now, only use pswitch: this should be good enough for all targets.
Change-Id: I0ae179e24555ac20c3d2bf2d267c1bb0e2ceded0
The old timrot setup API was very low-level and unfriendly. The new one
makes in easier to select the frequency source. Use to simplify timer
and kernel timer code.
Change-Id: Iffcdf11c00e925be9ec8d9a4efc74b197b6bd2aa
The adc channel monitored for jack detection does not really have a fixed
value when plugged. Instead use the same logic as the OF and simply use a
threshold.
Change-Id: I1d5270d83eb14decce29a39d8201ea1d1fb4436c
For some reason those targets have quite imprecise button voltages and the
old margin was too small. This should fix the button-not-working issue,
especially when the player is very hot and cold.
Change-Id: I9fcddd7f079cd1c4ee121567fb21a4a0cbc0562b
The current driver is limited to checking if the adc value equals another
one with a hardcoded margin. This commit changes two aspects of that:
- the margin can be changed globally using IMX233_BUTTON_LRADC_MARGIN
and can also be overriden per button using the new LRADC_EX macro
- the lradc logic gained two comparison modes to check if the source
value is greater (or lower) than a threshold.
Change-Id: If1614451dafeae818a96e6f23a84e6731331ba03
Shorten some text to make the text readable in the debug screen of
targets with small LCD (like NWZ-380). In some screens, the only
option is to display less information.
Change-Id: I78f8f35f7c507de19e5d27a918157504155f2ba6
The power management code was erroneously shuting down the 4.2V rail
when charging is complete. This resulted in the DCDC draining the battery
and thus the battery discharging with USB plugged...
The new code keeps the 4.2V rail active so that battery remains untouched
once charge is complete.
Change-Id: I36e8d31e8115c12ce813c939c5d7bbf2c3490157
NOTE: this commit does not introduce any change, ideally even the binary should
be almost the same. I checked the disassembly by hand and there are only a few
differences here and there, mostly the compiler decides to compile very close
expressions slightly differently. I tried to run the new code on several targets
to make sure and saw no difference.
The major syntax changes of the new headers are as follows:
- BF_{WR,SET,CLR} are now superpowerful and allows to set several fileds at once:
BF_WR(reg, field1(value1), field2(value2), ...)
- BF_CS (use like BF_WR) does a write to reg_CLR and then reg_SET instead of RMW
- there is no more need for macros like BF_{WR_,SET,CLR}_V, since one can simply
BF_WR with field_V(name)
- the old BF_SETV macro has no trivial equivalent and is replaced with its
its equivalent for BF_WR(reg_SET, ...)
I also rename the register headers: "regs/regs-x.h" -> "regs/x.h" to avoid the
redundant "regs".
Final note: the registers were generated using the following command:
./headergen_v2 -g imx -o ../../firmware/target/arm/imx233/regs/ desc/regs-stmp3{600,700,780}.xml
Change-Id: I7485e8b4315a0929a8edb63e7fa1edcaa54b1edc
- Speed auto detection is launched when an accessory is inserted,
so the user doesn't need to modify settings to use accessories
that operates at different speeds (or when the same accessory is
unplugged and plugged again).
- UART controller is disabled when no accessory is inserted, not
much powersave but everything counts.
Change-Id: If20c3617c2a87b6277fd7e0270031030c44fa953
This change ensures that Sansa Connect bootloader.bin will fit in its flash
partition.
Fix _flash_sizem calculation, division was not working properly because
FLASHSIZE included subtraction and defined value was not in parenthesis.
Prior to this change _flash_sizem was 0x00800000, now it is correctly set
to 4 in case of Sansa Connect and 8 in case of other TMS320DM320 players.
This significantly improves boot time as cache is now enabled only for
real flash memory region.
Change-Id: If3e50a3075c840dcb69dfafe5bba608a0acd2bf8
PMU interrupts are used to detect USB Vbus, wall adaptor, accessories
and holdswitch. A thread is needed to poll the PMU throught I2C, ATM
it does nothing but showing the state of the inputs on the HW debug
menu, funcionallity for each individual input will be added in next
patches.
Change-Id: If93bf2044d1052729237a7fd1431c8493e09f1c7
Do not rely on a bootloader initializing the HW, RB initializes
and configures GPIO, I2C, and PMU at startup.
Change-Id: If7f856b1f345f63de584aa4e4fc22d130cd66c80
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: If80214d26e505265ace19d9704f1e1300f98b2f4
When the bootloader starts, most of HW never has been initialized.
This patch includes all code needed to perform the preliminary
initialization on SYSCON, GPIO, i2c, and MIU.
The code is based on emCORE and OF reverse engineering, ported to
C for readability.
Change-Id: I9ecf2c3e8b1b636241a211dbba8735137accd05c
This patch optimizes UDMA timings to increase write transfer rate on
ATA bus, these transfers are clocked by HCLK, tDVS+tDVH is modified to
decrease Tcyctyp (typical write cycle period). This is not overclocking,
we meet the ATA standar, the settings used by OF are not well optimized
for each UDMA mode, we will never know but probably this was due some
documentation issue.
ATA_UDMA_TIME register is documented on s3c6400 datasheet, information
included in s5l8700 datasheet is wrong or not valid for s5l8702.
From ATA specs, (Minimum, Maximum) values in nanoseconds:
UDMA 0 UDMA 1 UDMA 2 UDMA 3 UDMA 4
tACKENV (20, 70) (20, 70) (20, 70) (20, 55) (20, 55)
tRP (160, --) (125, --) (100, --) (100, --) (100, --)
tSS (50, --) (50, --) (50, --) (50, --) (50, --)
tDVS (70, --) (48, --) (31, --) (20, --) (6.7, --)
tDVH (6.2, --) (6.2, --) (6.2, --) (6.2, --) (6.2, --)
tDVS+tDVH (120, --) (80, --) (60, --) (45, --) (30, --)
Tcyc = tDVS+tDVH
WR[bytes/s] = 1/Tcyc[s] * 2[bytes]
On Classic (boosted):
HClk = 108 MHz. -> T = ~9.26 ns.
Old values (used by OF):
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x5071152 27.8 166.7 55.6 74.1 55.6 129.7 15.4
1 0x3050a52 27.8 101.8 55.6 55.6 37 92.6 21.6
2 0x3030a52 27.8 101.8 55.6 37 37 74 27
3 0x2020a52 27.8 101.8 55.6 27.8 27.8 55.6 36
4 0x2010a52 27.8 101.8 55.6 18.5 27.8 46.3 43.2
New values:
UDMA ATA_UDMA_TIME tACK tRP tSS tDVS tDVH Tcyc WR(MB/s)
0 0x4071152 27.8 166.7 55.6 74.1 46.3 120.4 16.6
1 0x2050d52 27.8 129.6 55.6 55.6 27.8 83.4 24
2 0x2030a52 27.8 101.8 55.6 37 27.8 64.8 30.9
3 0x1020a52 27.8 101.8 55.6 27.8 18.5 46.3 43.2
4 0x1010a52 27.8 101.8 55.6 18.5 18.5 37 54
To verify that the settings are correct, a write-to-cache test was
performed using emCORE, the measured transfer rate (WRm) is compared
against the theoric transfer rate (WR) at 108 Mhz for the old and
the new UDMA4 settings (iPod 160, HDD Toshiba MK1634GAL):
UDMA ATA_UDMA_TIME Tcyc(ns) WR(MB/s) WRm(MB/s) RDm(MB/s)
4 0x2010a52 46.3 43.2 42.9 59.8
4 0x1010a52 37 54 53.5 59.8
Notes:
- The new UDMA4 settings increases ~25% the ATA transfer rate for
cached-writes. The real HDD write speed is limited by the internal
transfer rate (depends on cilinder, for the MK1634GAL it is 276 to
573 Mbits/s). Sequential write benchmark using diskdump on USB are
~8% faster.
- Read transfers are clocked by the device, it depends on UDMA mode
selected and are not affected by HClk or ATA_UDMA_TIME settings.
Read-from-cache tests results (RDm) using HClk=108 and HClk=54 for
UDMA4 are 59.8 MB/s on MK1634GAL.
- Minimum HClk is limited by tACKENV specs, using current settings
it is 54 MHz for UDMA4,UDMA3 and 43 MHz for UDMA2,UDMA1,UDMA0.
Change-Id: I61d67060410752518a59e1ff08072b21747ca997
When the bootloader starts only IRAM is available, the first task is to
ask the PMU to verify if the iPod has previously been hibernated by OF.
Due to memory limitations, the kernel cannot be used on this stage.
This patch modifies I2C and PMU low level functions to not to depend
on kernel (removes mutexes, and uses HW timer instead of current_tick),
actual kernel functions are modified to be 'mutexed' wrappers of the new
functions.
Change-Id: I7cef9e95dedaf176dc0659315f3dc33166d5b116
Add UART support for s5l8700/1 using the UC870X UART controller,
actually the functionallity is disabled and must be enabled for
each individual target. Tested on iPod Nano 2G (s5l8701), not
tested on s5l8700.
Change-Id: Ic0f216bb871502d355a70e4b658e536a2c0976a9
- Small rework on the UC8702 UART controller to make it compatible with
other s5l870x SOCs. Files moved and renamed, many conditional code
added to deal with capabilities and 'features' of the different CPUs.
- A couple of optimizacions that should not affect the functionality.
Change-Id: I705169f7e8b18d5d1da642f81ffc31c4089780a6
Interrupts version is cause of freeze on USB extraction.
Also non-interrupts version much simpler and faster.
Change-Id: I30a2993cdcaa85abfba77ca06bfacd5b6b4353e2
Voltage is reduced when the CPU is unboosted, resulting in a large
reduction in power consumption. In analogy with the AMSv1 voltage
scaling code (currently disabled due to problems with SD cards),
I have defined a config file option to enable/disable it.
Change-Id: Ia89c31ec06dd012354b4d53435e7b5b36243b206
We need additional delay since ascodec_write_pmu() working faster in
non-interrupts version of I2C2.
Change-Id: If4af3e42b3c8e8214baa36e54353b8adb527552d
After setting new PCLK (96 Mhz) we have too high DBOP (96 / 16 = 6 MHz).
According to datasheet DBOP should be maximum 4 MHz.
Change-Id: I1cbec054f41a76a6f18eadccb902c5b174ad6e3a
We should check sd_wait_for_tran_state() after transfering to prevent data
timeout error. Also we should disable DMA channel manually.
Should be used with g#1270, without it freezes still can occur on data
transfering.
Change-Id: If8c6e5547ab14d66237bccf65f83affc7a346e5e
With current setting we spend few minutes for reading one sector if we have
data timeout error. With new setting system (linux) show error after ~10 seconds.
Change-Id: Id3922acb2ea146c6ea2f89f26206df9488e6ee4e
