Commit graph

7 commits

Author SHA1 Message Date
Michael Sevakis
830531b7d4 i.MX31: Simplify nested interrupt handling. Give SVC mode its own stack by grabbing the FIQ stack that's just been taking up space. Just get rid of all FIQ setup since it isn't used anyway.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@30747 a1c6a512-1295-4272-9138-f99709370657
2011-10-14 00:01:41 +00:00
Michael Sevakis
60f843bf18 Configure Gigabeat S with EABI compiler by default. Implement the INIT section that this enables (due to selective need for long calls). Remove pcm_postinit from INIT section since it's asynchronous. Disable strict aliasing on SPC codec for now just to shut it up.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@26779 a1c6a512-1295-4272-9138-f99709370657
2010-06-11 14:39:35 +00:00
Michael Sevakis
affea5fe9e i.MX31: Make some style changes to some driver code so that hardware vs. variable access is more obvious to the eye. Change a few data types and qualifiers. No functional differences.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25865 a1c6a512-1295-4272-9138-f99709370657
2010-05-07 02:29:18 +00:00
Michael Sevakis
a36a498c57 i.MX31/Gigabeat S: This should fix stability problems. One problem was to start using the DVFS controller properly so that interrupts will be masked at the lowest and highest frequency indexes. Millions of useless interrupts were occurring at 132MHz because its index was 2, not 3, which masks it automatically when it can't go slower. Stopping the flood was enough to actually see the difference in general. IRQ must be disabled when fiddling with the CCM registers and only enabled when waiting for voltage ramp as having them enables also causes spurious DVFS ints. Implement interruptible ISR pro/epilogue more safely (always using IRQ stack even in SVC mode handling). Fix an improper inequality in DVFS code (which set regs for down when going up and v.v.). Misc. support changes. Have internal tables take less RAM.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25837 a1c6a512-1295-4272-9138-f99709370657
2010-05-06 03:23:51 +00:00
Michael Sevakis
b3f1eb8bba Gigabeat S: Those odd calls to irq_handler can still happen rarely after executing WFI. With no explanation forthcoming after trying many things, hide head in sand and ignore them and the IRQ will get vectored to the correct handler anyway. Have vector tables execute an immediate return and remove irq_handler from compilation altogether.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25792 a1c6a512-1295-4272-9138-f99709370657
2010-05-03 07:48:00 +00:00
Michael Sevakis
11cca264ff i.MX31/Gigabeat S: Implement frequency and voltage scaling-- 1.6V for 528MHz, and 1.35V for 264MHz and 132MHz. Keep DPTC overdrive ( > 400MHz) voltage scaling off for now because of uncertainties. Simplify the (working) mess later.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25699 a1c6a512-1295-4272-9138-f99709370657
2010-04-23 15:32:50 +00:00
Michael Sevakis
7abf2b53a4 Gigabeat S/i.MX31: Sort files in the /target tree into things that are SoC-generic (into /imx31) and player-specific (into /gigabeat-s, based upon current appearances). Move i2s clock init into the appropriate file. Housekeeping only-- no functional changes.
git-svn-id: svn://svn.rockbox.org/rockbox/trunk@25547 a1c6a512-1295-4272-9138-f99709370657
2010-04-09 01:21:53 +00:00
Renamed from firmware/target/arm/imx31/gigabeat-s/avic-imx31.c (Browse further)