This is a quick patch to solve FS#13104, we can not disable the
clickwheel LDO from within interrupt code, so for the moment we
leave it enabled all the time, it is unknown how power comsumption
is affected when the hold switch is locked.
Change-Id: I8f675702e2b5becbcd9197c8b044e6b8daeea79f
Somewhere along the line the screen stopped being cleared prior to
writing new text on each frame, which left visible bits of
previously-displayed text when it changed.
Change-Id: I344e03c234daa77f4e64ed89281c40db887e4498
Fix stuff that was bugging me about the way I did it at first.
While messing around I found RDS code wasn't masking its GPIO
ISR as it should, which might lead to two different interrupts
messing with the static data.
Change-Id: I54626809ea3039a842af0cc9e3e42853326c4193
Remove "low power mode clocking" as we stop clocking by hands after each transfer.
Remove CGU_IDE and CGU_MEMSTICK as we don't use them.
Simplify logic in sd_transfer_sectors.
Change-Id: I120396d7ec5c99c62f3a746306aa8edd8686e08a
Some drivers set tm_wday just fine and do not need it coerced to
be correct. Others set tm_yday, so don't overwrite what the driver
sets; just zero it inside if it can't fill the field. Move calls
to set_day_of_week() to the sorts of drivers that presumably
required the hammer (FS#11814) in get_time() where the weekday
isn't locked to the date.
Change-Id: Idd0ded6bfc9d9f48fcc1a6074068164c42fcf24a
1. Slightly revised and regularized internal interface. Callback is used
for read and write to provide completion signal instead of having two
mechanisms.
2. Lower overhead for asynchronous or alterate completion callbacks. We
now only init what is required by the transfer. A couple unneeded
structure members were also nixed.
3. Fixes a bug that would neglect a semaphore wait if pumping the I2C
interrupts in a loop when not in thread state or interrupts are masked.
4. Corrects broken initialization order by defining KDEV_INIT, which
makes kernel_init() call kernel_device_init() to initialize additional
devices _after_ the kernel, threading and synchronization objects are
safe to use.
5. Locking set_cpu_frequency has to be done at the highest level in
system.c to ensure the boost counter and the frequency are both set in
agreement. Reconcile the locking inteface between PP and AMS (the only
two currently using locking there) to keep it clean.
Now works fine with voltages in GIT HEAD on my Fuze v2, type 0.
Previously, everything crashed and died instantly. action.c calling
set_cpu_frequency from a tick was part of it. The rest may have been
related to 3. and 4. Honestly, I'm not certain!
Testing by Mihail Zenkov indicates it solves our problems. This will
get the developer builds running again after the kernel assert code
push.
Change-Id: Ie245994fb3e318dd5ef48e383ce61fdd977224d4
It handles GPIO and PWM based LEDs, possibly with several channels (red-green
LED for example). The debug allows one to play with the setting.
Currently the code supports the ZEN, ZEN X-Fi, and ZEN Mozaic.
Change-Id: I8c3b66e6ba21778acdb123daabb724280a7d1a4f
On STMP3700 there is no dedicated speaker amplifier but speaker is always on
lineout so it makes sense to report volume and power down of lineout.
Change-Id: If666bccf36d3a5ecc6d892823522d023f3206184
On PCM record initialization, an unknown clockgate is enabled instead
of the I2S clockgate. This bug does not produce incorrect functionallity
because the right clockgate is already enabled on PCM playback
initialization.
Change-Id: I97a3a4a6f12131e492c1431359a0a976b68014be
There are lot IRQ and most are unused most of the time, this is annoying on
devices with small screens.
Change-Id: I7f3453f2768b8e35a5a367fbcf1e4cf3cf73bcd7
Those new statistics give the maximum time an IRQ took and also the total
time spent in IRQ, for each IRQ. Hopefully those do not take took much time
or space to collect. If this is the case, it can be enabled in debug builds only
the future.
Change-Id: I05af172897c5cb7ffcc9322452f974d8f968e29d
The IRQ handler saves registers on the IRQ stack, saves the old PC to imx233
HW_DIGCTL_SCRATCH0 register and switcht to SVC for the actual handling. The
old code had a problem in that if the unwinder is called during the IRQ (for
example by the watchdog), then __get_sp() will use SPSR_svc to discover the
previous mode, switch to it and recover SP. But SPSR_svc is invalid, it should
be SPSR_irq but we switch from IRQ to SVC mode. The new code copies SPSR_irq
to SPSR_svc in IRQ to fix this problem. It also saves/restore SCRATCH0 in
case I one day renable nested interrupts or use SCRATCH0 for other purposes.
I also changed the old watchdog code to call UIE directly instead of trying
to make the code crash with a SWI.
Change-Id: Id87462d410764b019bd2aa9adc71cb917ade32e3
The old code made the setting appear as 0dB, 1.5dB, 3dB and 4.5dB when
in fact it is 0dB, 3dB, 4.5dB and 6dB. This commit clarifies the code and
also fix this at the same time. This imx233 3D enhancement is complete crap anyway
but now you can satisfy yourself with 6 dB of pure crap, clearly an enhancement.
Change-Id: Ia3e088987c1ff0cdde228905ff70f46476a499a2
This commit adds the necessary code in the dualboot stub (bootloader) to
let rockbox control the boot process. In particular, rockbox can now choose
if the next boot will be normal (boot rockbox or OF on magic key), to OF
or to updater.
The intents (to be added in follow-up commits) are:
1) Let the user more easily reboot to the OF. On some targets it is not trivial,
especially in USB mode.
2) Automatically reboot to updater when the user drop firmware.sb at the root
of the drive (currently, the user needs to do that in OF USB mode)
3) Document this OF magic
Change-Id: I86df651dec048c318c6a22de74abb8c6b41aa9ad
This clearly fixes recording on targets where the bias pin was wrong. It may
also improve recording on targets where the bias voltage was wrong. I was unable
to find those parameters on the ZEN Mozaic, which fallback to default values.
Change-Id: Ifb5f823c9cbd01f0d9a80fa5d49d93972c8b7cfe
For some reason, there was a mismatch between the setting (decibel) and the
audiohw code (centicel). This resulted in a gain divided by 10. This may
explain why some people experienced low volume with the mic on the fuze+.
Change-Id: I138ac18dd93c36f43a7dfce735efc826405c598c
Based on emCORE.
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: I3c616ded42260c6626bda23b7e580791981df61d
Based on emCORE.
Low level functions that do not depend on Rockbox kernel,
intended to be used by the bootloader, dualboot-installer,
RB drivers or other .dfu tools.
Change-Id: Iad369627b55bf1778eab437424072f1a653e4db6
- Some rewrite with the intent to get ride of these random errors
appearing on some builds/devices (not much noticeable on RB but
can ruin bootloader builds).
- Error handling (ACK).
- IIC clock increased to be the same as in OF.
Change-Id: Idf8cfa3c230a0a61ec9c879bf6f0ea8b061a4607
Add code to read USB D+/D- and accessory ADCs, it is shown in HW
debug menu, might be useful in future for RB and/or the bootloader
to identify external USB chargers.
Change-Id: Ia48ca5e06bb7ddc52bb55abedde6734653ce8dba
Based on g#844 and g#949, it is intended as a replacement for the
current s3c6400x USB driver.
The DesignWare USB OTG core is integrated into many SoC's, however
HW core version and capabilities (mainly DMA mode, Tx FIFO mode,
FIFO size and number of available IN/OUT endpoins) may differ:
CPU targets HW ver DMA NPTX FIFO FIFO sz #IN/OUT
-------- ------------- ------ --- --------- ------- -------
as3525v2 sansaclipplus 2.60a Yes Dedicated 0x535 4/4
sansaclipv2
sansaclipzip
sansafuzev2
s5l8701 ipodnano2g 2.20a Yes Shared 0x500 4/5
s5l8702 ipod6g 2.60a Yes Dedicated 0x820 7/7
ipodnano3g
s5l8720 ipodnano4g ? ? ? ? ?
Functionality supported by this driver:
- Device mode, compatible with USB 1.1/2.0 hosts.
- Shared FIFO (USB_DW_SHARED_FIFO) or dedicated FIFOs.
- No DMA (USB_DW_ARCH_SLAVE) or internal DMA mode.
- Concurrent transfers: control, bulk (usb_storage, usb_serial) and
interrupt (usb_hid).
Actually this driver is not used by any CPU, it will be enabled for
each individual CPU/target in next patches.
Change-Id: I74a1e836d18927a31f6977d71115fb442477dd5f
Apparently I simply forgot to calibrate it when the port was done and the
current values are just plain wrong, especially for the charging curve.
Change-Id: Ied3cafa52f31f182f953714e28edc4c5e891255f
There are two very suspicious things in the power off code:
- it does not properly unlock the power register, so it should fail (!)
- it does not disable sw/hw watchdog so if register fails, the device will
most probably crash horribly because of the watchdog
I don't even understand how it worked before.
Change-Id: I9f3f94bd012e52c3b50cd5b658d68b5eb907f79b
The old driver was bad in many respect, it had some race conditions, it was
using a thread to serialize transfers because of the legacy i2c interface.
It also had huge latency (typically 50ms but delays up to 300ms can happen),
thus some presses were missed.
The new driver takes advantage of the new i2c driver to do everything
asynchronously. It also does not need a thread anymore because queueing
ensures proper serialization. It provides much better and reliable latency
(typically ~2ms).
Also fix the debug screen which was horribly broken. The new screen also
displays the deadzones.
Change-Id: I69b7f99b75053e6b1d3d56beb4453c004fd2076e
The new driver provides several new features:
- asynchronous transfer
- transactions (several transfers executed at once)
- queueing
The style still provides the legacy interface.
Change-Id: I6d8ecc89d1f7057847c9b2dc69b76cd45c9c8407
Always enable support for SET_BLOCK_COUNT on mmc: it is mandatory. For some
reason (probably a mistake) it was disabled unconditionaly on mmc.
Also deselect sd card after init. Although it is unlikely to make a difference,
it is already done for mmc so stay consistent.
Change-Id: I276f0d95f5bb6a0bf431c2fff4589d3dfb15f8c7
