iPod Classic: rework on I2C driver
- Some rewrite with the intent to get ride of these random errors appearing on some builds/devices (not much noticeable on RB but can ruin bootloader builds). - Error handling (ACK). - IIC clock increased to be the same as in OF. Change-Id: Idf8cfa3c230a0a61ec9c879bf6f0ea8b061a4607
This commit is contained in:
Cástor Muñoz
parent
adbd2969e6
commit
578525b463
3 changed files with 153 additions and 144 deletions
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@ -196,6 +196,20 @@
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#define I2CCLKGATE(i) ((i) == 1 ? CLOCKGATE_I2C1 : \
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CLOCKGATE_I2C0)
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/* s5l8702 I2C controller is similar to s5l8700, known differences are:
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* IICCON[5] is not used in s5l8702.
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* IICCON[13:8] are used to enable interrupts.
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IICSTA2[13:8] are used to read the status and write-clear interrupts.
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Known interrupts:
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[13] STOP on bus (TBC)
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[12] START on bus (TBC)
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[8] byte transmited or received in Master mode (not tested in Slave)
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* IICCON[4] does not clear interrupts, it is enabled when a byte is
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transmited or received, in Master mode the tx/rx of the next byte
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starts when it is written as "1".
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*/
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#define IICCON(bus) (*((uint32_t volatile*)(0x3C600000 + 0x300000 * (bus))))
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#define IICSTAT(bus) (*((uint32_t volatile*)(0x3C600004 + 0x300000 * (bus))))
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#define IICADD(bus) (*((uint32_t volatile*)(0x3C600008 + 0x300000 * (bus))))
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@ -203,6 +217,7 @@
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#define IICUNK10(bus) (*((uint32_t volatile*)(0x3C600010 + 0x300000 * (bus))))
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#define IICUNK14(bus) (*((uint32_t volatile*)(0x3C600014 + 0x300000 * (bus))))
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#define IICUNK18(bus) (*((uint32_t volatile*)(0x3C600018 + 0x300000 * (bus))))
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#define IICSTA2(bus) (*((uint32_t volatile*)(0x3C600020 + 0x300000 * (bus))))
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/////INTERRUPT CONTROLLERS/////
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@ -144,8 +144,6 @@ bool dbg_hw_info(void)
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_DEBUG_PRINTF("USB D+: %d mV", adc_read_usbdata_voltage(true));
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_DEBUG_PRINTF("USB D-: %d mV", adc_read_usbdata_voltage(false));
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line++;
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extern unsigned long i2c_rd_err, i2c_wr_err;
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_DEBUG_PRINTF("i2c rd/wr errors: %lu/%lu", i2c_rd_err, i2c_wr_err);
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}
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#ifdef UC870X_DEBUG
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else if(state==(max_states-1))
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@ -25,173 +25,174 @@
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#include "i2c-s5l8702.h"
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#include "clocking-s5l8702.h"
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/* Driver for the s5l8700 built-in I2C controller in master mode
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/* Driver for the s5l8702 built-in I2C controller in master mode
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Both the i2c_read and i2c_write function take the following arguments:
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* slave, the address of the i2c slave device to read from / write to
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* address, optional sub-address in the i2c slave (unused if -1)
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* len, number of bytes to be transfered
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* data, pointer to data to be transfered
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A return value < 0 indicates an error.
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A return value > 0 indicates an error.
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Note:
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* blocks the calling thread for the entire duraton of the i2c transfer but
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uses wakeup_wait/wakeup_signal to allow other threads to run.
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* ACK from slave is not checked, so functions never return an error
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Fixme:
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* actually there is no STOP + i2c_off() on error
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* very rare random errors when reading and/or(?) writing registers on some
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builds/devices, hard to trace, not a 'delay' issue, it seems related
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with alignment of STRs and/or(?) LDRs, code cache lines, pipelines...
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The new code tries to mix STRs and LDRs at some points but ATM it is
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unknown if it might solve or mitigate the problem. Probably it could be
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really fixed using wait_rdy() before accessing any register, as OF does.
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*/
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/* s5l8702 I2C controller is similar to s5l8700, known differences are:
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* IICCON[5] is not used in s5l8702.
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* IICCON[13:8] are used to enable interrupts.
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IICUNK20[13:8] are used to read the status and write-clear interrupts.
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Known interrupts:
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[13] STOP on bus (TBC)
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[12] START on bus (TBC)
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[8] byte transmited or received in Master mode (not tested in Slave)
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* IICCON[4] does not clear interrupts, it is enabled when a byte is
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transmited or received, in Master mode the tx/rx of the next byte
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starts when it is written as "1".
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* blocks the calling thread for the entire duraton of the i2c transfer.
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*/
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static struct mutex i2c_mtx[2];
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static void i2c_on(int bus)
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{
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/* enable I2C clock */
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clockgate_enable(I2CCLKGATE(bus), true);
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IICCON(bus) = (0 << 8) | /* INT_EN = disabled */
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(1 << 7) | /* ACK_GEN */
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(0 << 6) | /* CLKSEL = PCLK/16 */
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(7 << 0); /* CK_REG */
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/* serial output on */
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IICSTAT(bus) = (1 << 4);
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}
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static void i2c_off(int bus)
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{
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/* serial output off */
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IICSTAT(bus) = 0;
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/* disable I2C clock */
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clockgate_enable(I2CCLKGATE(bus), false);
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}
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void i2c_init()
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{
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mutex_init(&i2c_mtx[0]);
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mutex_init(&i2c_mtx[1]);
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}
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static void wait_rdy(int bus)
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{
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while (IICUNK10(bus));
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}
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static void i2c_on(int bus)
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{
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/* enable I2C clock */
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clockgate_enable(I2CCLKGATE(bus), true);
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}
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static void i2c_off(int bus)
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{
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/* serial output off */
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wait_rdy(bus);
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IICSTAT(bus) = 0;
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/* disable I2C clock */
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wait_rdy(bus);
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clockgate_enable(I2CCLKGATE(bus), false);
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}
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/* wait for bus not busy, or tx/rx byte (should return once
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8 data + 1 ack clocks are generated), or STOP. */
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static void i2c_wait_io(int bus)
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{
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while (((IICSTAT(bus) & (1 << 5)) != 0) &&
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((IICSTA2(bus) & ((1 << 8)|(1 << 13))) == 0)) {
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wait_rdy(bus);
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}
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IICSTA2(bus) |= (1 << 8)|(1 << 13);
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}
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static int i2c_start(int bus, unsigned char slave, bool rd)
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{
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/* configure port */
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wait_rdy(bus);
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IICCON(bus) = (0 << 8) | /* INT_EN = disabled */
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(1 << 7) | /* ACK_GEN */
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(0 << 6) | /* CLKSEL = PCLK/32 (TBC) */
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(4 << 0); /* CK_REG */
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/* START */
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wait_rdy(bus);
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IICDS(bus) = slave | rd;
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wait_rdy(bus);
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IICSTAT(bus) = rd ? 0xB0 : 0xF0;
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i2c_wait_io(bus);
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/* check ACK */
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if (IICSTAT(bus) & 1)
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return 1;
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return 0;
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}
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static void i2c_stop(int bus)
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{
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/* STOP */
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wait_rdy(bus);
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IICSTAT(bus) &= ~0x20;
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wait_rdy(bus);
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IICCON(bus) = 0x10;
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i2c_wait_io(bus);
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}
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static int i2c_wr_internal(int bus, unsigned char slave,
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int address, int len, const unsigned char *data)
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{
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int rc = 0;
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if (i2c_start(bus, slave, false) == 0)
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{
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/* write address + data */
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const unsigned char *ptr = data;
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const unsigned char addr = address;
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if (address >= 0) {
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ptr = &addr;
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len++;
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}
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while (len--) {
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wait_rdy(bus);
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IICDS(bus) = *ptr;
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udelay(5);
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wait_rdy(bus);
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IICCON(bus) = IICCON(bus);
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i2c_wait_io(bus);
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/* check ACK */
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if (IICSTAT(bus) & 1) {
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rc = 2;
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break;
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}
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if (ptr == &addr) ptr = data;
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else ptr++;
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}
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}
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else
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rc = 1;
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i2c_stop(bus);
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return rc;
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}
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static int i2c_rd_internal(int bus, unsigned char slave, int len, unsigned char *data)
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{
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int rc = 0;
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if (i2c_start(bus, slave, true) == 0)
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{
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while (len--) {
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wait_rdy(bus);
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IICCON(bus) &= ~(len ? 0 : 0x80); /* ACK or NAK */
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i2c_wait_io(bus);
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*data++ = IICDS(bus);
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}
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}
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else
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rc = 3;
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i2c_stop(bus);
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return rc;
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}
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int i2c_wr(int bus, unsigned char slave, int address, int len, const unsigned char *data)
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{
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i2c_on(bus);
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long timeout = USEC_TIMER + 20000;
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/* START */
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IICDS(bus) = slave & ~1;
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IICSTAT(bus) = 0xF0;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 1;
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if (address >= 0) {
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/* write address */
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IICDS(bus) = address;
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IICCON(bus) = IICCON(bus);
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 2;
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}
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/* write data */
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while (len--) {
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IICDS(bus) = *data++;
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IICCON(bus) = IICCON(bus);
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 4;
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}
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/* STOP */
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IICSTAT(bus) = 0xD0;
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IICCON(bus) = IICCON(bus);
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while ((IICSTAT(bus) & (1 << 5)) != 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 5;
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int rc = i2c_wr_internal(bus, slave, address, len, data);
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i2c_off(bus);
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return 0;
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return rc;
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}
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int i2c_rd(int bus, unsigned char slave, int address, int len, unsigned char *data)
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{
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i2c_on(bus);
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long timeout = USEC_TIMER + 20000;
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if (address >= 0) {
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/* START */
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IICDS(bus) = slave & ~1;
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IICSTAT(bus) = 0xF0;
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 1;
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/* write address */
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IICDS(bus) = address;
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IICCON(bus) = IICCON(bus);
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 2;
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}
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/* (repeated) START */
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IICDS(bus) = slave | 1;
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IICSTAT(bus) = 0xB0;
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IICCON(bus) = IICCON(bus);
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 3;
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while (len--) {
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IICCON(bus) &= ~(len ? 0 : 0x80); /* ACK or NAK */
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while ((IICCON(bus) & 0x10) == 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 4;
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*data++ = IICDS(bus);
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}
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/* STOP */
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IICSTAT(bus) = 0x90;
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IICCON(bus) = IICCON(bus);
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while ((IICSTAT(bus) & (1 << 5)) != 0)
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if (TIME_AFTER(USEC_TIMER, timeout))
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return 5;
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int rc = i2c_wr_internal(bus, slave, address, 0, NULL);
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if (rc == 0)
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rc = i2c_rd_internal(bus, slave, len, data);
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i2c_off(bus);
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return 0;
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return rc;
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}
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unsigned long i2c_rd_err, i2c_wr_err;
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int i2c_write(int bus, unsigned char slave, int address, int len, const unsigned char *data)
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{
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int ret;
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mutex_lock(&i2c_mtx[bus]);
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ret = i2c_wr(bus, slave, address, len, data);
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mutex_unlock(&i2c_mtx[bus]);
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if (ret) i2c_wr_err++;
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return ret;
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}
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@ -201,18 +202,14 @@ int i2c_read(int bus, unsigned char slave, int address, int len, unsigned char *
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mutex_lock(&i2c_mtx[bus]);
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ret = i2c_rd(bus, slave, address, len, data);
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mutex_unlock(&i2c_mtx[bus]);
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if (ret) i2c_rd_err++;
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return ret;
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}
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static void wait_rdy(int bus)
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{
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while (IICUNK10(bus));
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}
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void i2c_preinit(int bus)
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{
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clockgate_enable(I2CCLKGATE(bus), true);
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if (bus == 0) PCON3 = (PCON3 & ~0x00000ff0) | 0x00000220;
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/* TBC: else if(bus == 1) PCON6 = (PCON6 & ~0x0ff00000) | 0x02200000; */
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i2c_on(bus);
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wait_rdy(bus);
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IICADD(bus) = 0x40; /* own slave address */
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wait_rdy(bus);
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@ -220,11 +217,10 @@ void i2c_preinit(int bus)
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wait_rdy(bus);
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IICUNK18(bus) = 0;
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wait_rdy(bus);
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IICSTAT(bus) = 0x80; /* master Rx mode, Tx/Rx off */
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IICSTAT(bus) = 0x80; /* master Rx mode, serial output off */
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wait_rdy(bus);
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IICCON(bus) = 0;
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wait_rdy(bus);
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IICSTAT(bus) = 0; /* slave Rx mode, Tx/Rx off */
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wait_rdy(bus);
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clockgate_enable(I2CCLKGATE(bus), false);
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IICSTA2(bus) = 0x3f00;
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i2c_off(bus);
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}
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